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| author | Craig Topper <craig.topper@gmail.com> | 2013-08-14 07:04:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-08-14 07:04:42 +0000 |
| commit | f3d98a882e1cc426001adafafa440b69143d83e8 (patch) | |
| tree | 4a4dac24069049ea62602d26064e6c0e3e9525dc /lib/Target | |
| parent | d36b53e764b742c2ba16ae2b2517646694e05bff (diff) | |
| download | external_llvm-f3d98a882e1cc426001adafafa440b69143d83e8.zip external_llvm-f3d98a882e1cc426001adafafa440b69143d83e8.tar.gz external_llvm-f3d98a882e1cc426001adafafa440b69143d83e8.tar.bz2 | |
Use MVT in more lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188363 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index f73689d..6253b33 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4789,7 +4789,7 @@ static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { /// getLegalSplat - Generate a legal splat with supported x86 shuffles static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { - EVT VT = V.getValueType(); + MVT VT = V.getValueType().getSimpleVT(); SDLoc dl(V); if (VT.is128BitVector()) { @@ -4815,7 +4815,7 @@ static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { /// PromoteSplat - Splat is promoted to target supported vector shuffles. static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { - EVT SrcVT = SV->getValueType(0); + MVT SrcVT = SV->getValueType(0).getSimpleVT(); SDValue V1 = SV->getOperand(0); SDLoc dl(SV); @@ -4838,7 +4838,7 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { // instruction because the target has no such instruction. Generate shuffles // which repeat i16 and i8 several times until they fit in i32, and then can // be manipulated by target suported shuffles. - EVT EltVT = SrcVT.getVectorElementType(); + MVT EltVT = SrcVT.getVectorElementType(); if (EltVT == MVT::i8 || EltVT == MVT::i16) V1 = PromoteSplati8i16(V1, DAG, EltNo); @@ -4860,7 +4860,7 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool IsZero, const X86Subtarget *Subtarget, SelectionDAG &DAG) { - EVT VT = V2.getValueType(); + MVT VT = V2.getValueType().getSimpleVT(); SDValue V1 = IsZero ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT); unsigned NumElems = VT.getVectorNumElements(); @@ -5563,7 +5563,7 @@ X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const { SDValue X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const { - EVT VT = Op.getValueType(); + MVT VT = Op.getValueType().getSimpleVT(); // Skip if insert_vec_elt is not supported. if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) @@ -5639,7 +5639,7 @@ X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const { SDValue X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const { - EVT VT = Op.getValueType(); + MVT VT = Op.getValueType().getSimpleVT(); assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) && "Unexpected type in LowerBUILD_VECTORvXi1!"); |