What should be the last unnecessary <iostream>s in the library.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8

34 files changed, 119 insertions, 158 deletions

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index b85cfa2..e57a768 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -31,7 +31,6 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MathExtras.h"
 #include <cctype>
-#include <iostream>
 using namespace llvm;
 
 namespace {
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index cf02b8b..08864a7 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -27,7 +27,6 @@
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Support/Debug.h"
-#include <iostream>
 #include <vector>
 using namespace llvm;
 
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 09c8b1f..027b193 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -24,7 +24,6 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
 // hasFP - Return true if the specified function should have a dedicated frame
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index f4540db..4b71ab5 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -24,7 +24,6 @@
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/ADT/Statistic.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -105,7 +104,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
     return;
 
   case MachineOperand::MO_Immediate:
-    std::cerr << "printOp() does not handle immediate values\n";
+    cerr << "printOp() does not handle immediate values\n";
     abort();
     return;
 
@@ -265,13 +264,13 @@ bool AlphaAsmPrinter::doFinalization(Module &M) {
                               "\t.section .data", I);
           break;
         case GlobalValue::GhostLinkage:
-          std::cerr << "GhostLinkage cannot appear in AlphaAsmPrinter!\n";
+          cerr << "GhostLinkage cannot appear in AlphaAsmPrinter!\n";
           abort();
         case GlobalValue::DLLImportLinkage:
-          std::cerr << "DLLImport linkage is not supported by this target!\n";
+          cerr << "DLLImport linkage is not supported by this target!\n";
           abort();
         case GlobalValue::DLLExportLinkage:
-          std::cerr << "DLLExport linkage is not supported by this target!\n";
+          cerr << "DLLExport linkage is not supported by this target!\n";
           abort();
         default:
           assert(0 && "Unknown linkage type!");
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp
index 884215e..6f5bc70 100644
--- a/lib/Target/Alpha/AlphaCodeEmitter.cpp
+++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp
@@ -23,7 +23,6 @@
 #include "llvm/Function.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/ADT/Statistic.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -158,7 +157,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
     rv = MO.getImmedValue();
   } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
              || MO.isConstantPoolIndex()) {
-    DEBUG(std::cerr << MO << " is a relocated op for " << MI << "\n";);
+    DOUT << MO << " is a relocated op for " << MI << "\n";
     unsigned Reloc = 0;
     int Offset = 0;
     bool useGOT = false;
@@ -214,7 +213,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
                                                Alpha::reloc_bsr,
                                                MO.getMachineBasicBlock()));
   }else {
-    std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
+    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
     abort();
   }
 
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index 521e661..fc752aa 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -29,7 +29,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
-#include <iostream>
 #include <queue>
 #include <set>
 using namespace llvm;
@@ -115,7 +114,7 @@ namespace {
       unsigned at = CountLeadingZeros_64(x);
       uint64_t complow = 1 << (63 - at);
       uint64_t comphigh = 1 << (64 - at);
-      //std::cerr << x << ":" << complow << ":" << comphigh << "\n";
+      //cerr << x << ":" << complow << ":" << comphigh << "\n";
       if (abs(complow - x) <= abs(comphigh - x))
         return complow;
       else
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 6d53a9e..3ea4e88 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -22,8 +22,6 @@
 #include "llvm/Function.h"
 #include "llvm/Module.h"
 #include "llvm/Support/CommandLine.h"
-#include <iostream>
-
 using namespace llvm;
 
 /// AddLiveIn - This helper function adds the specified physical register to the
@@ -224,7 +222,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
     if (ArgNo  < 6) {
       switch (ObjectVT) {
       default:
-        std::cerr << "Unknown Type " << ObjectVT << "\n";
+        cerr << "Unknown Type " << ObjectVT << "\n";
         abort();
       case MVT::f64:
         args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], 
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 4ac352b..71bf5b0 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -15,7 +15,6 @@
 #include "AlphaInstrInfo.h"
 #include "AlphaGenInstrInfo.inc"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include <iostream>
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()
diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp
index 81f5e74..669a2d5 100644
--- a/lib/Target/Alpha/AlphaJITInfo.cpp
+++ b/lib/Target/Alpha/AlphaJITInfo.cpp
@@ -18,7 +18,6 @@
 #include "llvm/Config/alloca.h"
 #include "llvm/Support/Debug.h"
 #include <cstdlib>
-#include <iostream>
 #include <map>
 using namespace llvm;
 
@@ -58,12 +57,12 @@ static void EmitBranchToAt(void *At, void *To) {
 
   AtI[0] = BUILD_OR(0, 27, 27);
 
-  DEBUG(std::cerr << "Stub targeting " << To << "\n");
+  DOUT << "Stub targeting " << To << "\n";
 
   for (int x = 1; x <= 8; ++x) {
     AtI[2*x - 1] = BUILD_SLLi(27,27,8);
     unsigned d = (Fn >> (64 - 8 * x)) & 0x00FF;
-    //    DEBUG(std::cerr << "outputing " << hex << d << dec << "\n");
+    //DOUT << "outputing " << hex << d << dec << "\n";
     AtI[2*x] = BUILD_ORi(27, 27, d);
   }
   AtI[17] = BUILD_JMP(31,27,0); //jump, preserving ra, and setting pv
@@ -87,12 +86,12 @@ extern "C" {
 
     //rewrite the stub to an unconditional branch
     if (((unsigned*)CameFromStub)[18] == 0x00FFFFFF) {
-      DEBUG(std::cerr << "Came from a stub, rewriting\n");
+      DOUT << "Came from a stub, rewriting\n";
       EmitBranchToAt(CameFromStub, Target);
     } else {
-      DEBUG(std::cerr << "confused, didn't come from stub at " << CameFromStub
-            << " old jump vector " << oldpv
-            << " new jump vector " << Target << "\n");
+      DOUT << "confused, didn't come from stub at " << CameFromStub
+           << " old jump vector " << oldpv
+           << " new jump vector " << Target << "\n";
     }
 
     //Change pv to new Target
@@ -185,7 +184,7 @@ extern "C" {
       );
 #else
   void AlphaCompilationCallback() {
-    std::cerr << "Cannot call AlphaCompilationCallback() on a non-Alpha arch!\n";
+    cerr << "Cannot call AlphaCompilationCallback() on a non-Alpha arch!\n";
     abort();
   }
 #endif
@@ -199,7 +198,7 @@ void *AlphaJITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
   for (int x = 0; x < 19; ++ x)
     MCE.emitWordLE(0);
   EmitBranchToAt(Addr, Fn);
-  DEBUG(std::cerr << "Emitting Stub to " << Fn << " at [" << Addr << "]\n");
+  DOUT << "Emitting Stub to " << Fn << " at [" << Addr << "]\n";
   return MCE.finishFunctionStub(0);
 }
 
@@ -250,30 +249,30 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
     case Alpha::reloc_literal:
       //This is a LDQl
       idx = MR->getGOTIndex();
-      DEBUG(std::cerr << "Literal relocation to slot " << idx);
+      DOUT << "Literal relocation to slot " << idx;
       idx = (idx - GOToffset) * 8;
-      DEBUG(std::cerr << " offset " << idx << "\n");
+      DOUT << " offset " << idx << "\n";
       break;
     case Alpha::reloc_gprellow:
       idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
       idx = getLower16(idx);
-      DEBUG(std::cerr << "gprellow relocation offset " << idx << "\n");
-      DEBUG(std::cerr << " Pointer is " << (void*)MR->getResultPointer()
-            << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
+      DOUT << "gprellow relocation offset " << idx << "\n";
+      DOUT << " Pointer is " << (void*)MR->getResultPointer()
+           << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n";
       break;
     case Alpha::reloc_gprelhigh:
       idx = (unsigned char*)MR->getResultPointer() - &GOTBase[GOToffset * 8];
       idx = getUpper16(idx);
-      DEBUG(std::cerr << "gprelhigh relocation offset " << idx << "\n");
-      DEBUG(std::cerr << " Pointer is " << (void*)MR->getResultPointer()
-            << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n");
+      DOUT << "gprelhigh relocation offset " << idx << "\n";
+      DOUT << " Pointer is " << (void*)MR->getResultPointer()
+           << " GOT is " << (void*)&GOTBase[GOToffset * 8] << "\n";
       break;
     case Alpha::reloc_gpdist:
       switch (*RelocPos >> 26) {
       case 0x09: //LDAH
         idx = &GOTBase[GOToffset * 8] - (unsigned char*)RelocPos;
         idx = getUpper16(idx);
-        DEBUG(std::cerr << "LDAH: " << idx << "\n");
+        DOUT << "LDAH: " << idx << "\n";
         //add the relocation to the map
         gpdistmap[std::make_pair(Function, MR->getConstantVal())] = RelocPos;
         break;
@@ -283,7 +282,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR,
         idx = &GOTBase[GOToffset * 8] -
           (unsigned char*)gpdistmap[std::make_pair(Function, MR->getConstantVal())];
         idx = getLower16(idx);
-        DEBUG(std::cerr << "LDA: " << idx << "\n");
+        DOUT << "LDA: " << idx << "\n";
         break;
       default:
         assert(0 && "Cannot handle gpdist yet");
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 02d1570..bafd3b3 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -30,7 +30,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
-#include <iostream>
 using namespace llvm;
 
 //These describe LDAx
@@ -63,8 +62,8 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx,
                                        const TargetRegisterClass *RC) const {
-  //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
-  //<< FrameIdx << "\n";
+  //cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
+  //     << FrameIdx << "\n";
   //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
   if (RC == Alpha::F4RCRegisterClass)
     BuildMI(MBB, MI, TII.get(Alpha::STS))
@@ -84,8 +83,8 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         unsigned DestReg, int FrameIdx,
                                         const TargetRegisterClass *RC) const {
-  //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to "
-  //<< FrameIdx << "\n";
+  //cerr << "Trying to load " << getPrettyName(DestReg) << " to "
+  //     << FrameIdx << "\n";
   if (RC == Alpha::F4RCRegisterClass)
     BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
@@ -139,7 +138,7 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator MI,
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *RC) const {
-  //  std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
+  //cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n";
   if (RC == Alpha::GPRCRegisterClass) {
     BuildMI(MBB, MI, TII.get(Alpha::BISr), DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == Alpha::F4RCRegisterClass) {
@@ -147,8 +146,8 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   } else if (RC == Alpha::F8RCRegisterClass) {
     BuildMI(MBB, MI, TII.get(Alpha::CPYST), DestReg).addReg(SrcReg).addReg(SrcReg);
   } else {
-    std::cerr << "Attempt to copy register that is not GPR or FPR";
-     abort();
+    cerr << "Attempt to copy register that is not GPR or FPR";
+    abort();
   }
 }
 
@@ -255,16 +254,16 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
   // Now add the frame object offset to the offset from the virtual frame index.
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
 
-  DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n");
+  DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n";
 
   Offset += MF.getFrameInfo()->getStackSize();
 
-  DEBUG(std::cerr << "Corrected Offset " << Offset <<
-        " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n");
+  DOUT << "Corrected Offset " << Offset
+       << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n";
 
   if (Offset > IMM_HIGH || Offset < IMM_LOW) {
-    DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: "
-          << Offset << "\n");
+    DOUT << "Unconditionally using R28 for evil purposes Offset: "
+         << Offset << "\n";
     //so in this case, we need to use a temporary register, and move the
     //original inst off the SP/FP
     //fix up the old:
@@ -309,8 +308,8 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
     // brackets around call sites.
     //If there is a frame pointer, then we don't do this
     NumBytes += MFI->getMaxCallFrameSize();
-    DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize()
-          << " to the stack due to calls\n");
+    DOUT << "Added " << MFI->getMaxCallFrameSize()
+         << " to the stack due to calls\n";
   }
 
   if (FP)
@@ -336,7 +335,7 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
     BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30).addImm(getLower16(NumBytes))
       .addReg(Alpha::R30);
   } else {
-    std::cerr << "Too big a stack frame at " << NumBytes << "\n";
+    cerr << "Too big a stack frame at " << NumBytes << "\n";
     abort();
   }
 
@@ -386,7 +385,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
          BuildMI(MBB, MBBI, TII.get(Alpha::LDA), Alpha::R30)
            .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
        } else {
-         std::cerr << "Too big a stack frame at " << NumBytes << "\n";
+         cerr << "Too big a stack frame at " << NumBytes << "\n";
          abort();
        }
      }
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index d8fe0e8..7c0d433 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -42,9 +42,7 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Config/config.h"
 #include <algorithm>
-#include <iostream>
 #include <ios>
-#include <sstream>
 using namespace llvm;
 
 namespace {
@@ -229,7 +227,7 @@ namespace {
     void visitVAArgInst (VAArgInst &I);
 
     void visitInstruction(Instruction &I) {
-      std::cerr << "C Writer does not know about " << I;
+      cerr << "C Writer does not know about " << I;
       abort();
     }
 
@@ -375,7 +373,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty,
     case Type::FloatTyID:  return Out << "float "              << NameSoFar;
     case Type::DoubleTyID: return Out << "double "             << NameSoFar;
     default :
-      std::cerr << "Unknown primitive type: " << *Ty << "\n";
+      cerr << "Unknown primitive type: " << *Ty << "\n";
       abort();
     }
 
@@ -726,8 +724,8 @@ void CWriter::printConstant(Constant *CPV) {
     }
 
     default:
-      std::cerr << "CWriter Error: Unhandled constant expression: "
-                << *CE << "\n";
+      cerr << "CWriter Error: Unhandled constant expression: "
+           << *CE << "\n";
       abort();
     }
   } else if (isa<UndefValue>(CPV) && CPV->getType()->isFirstClassType()) {
@@ -901,7 +899,7 @@ void CWriter::printConstant(Constant *CPV) {
     }
     // FALL THROUGH
   default:
-    std::cerr << "Unknown constant type: " << *CPV << "\n";
+    cerr << "Unknown constant type: " << *CPV << "\n";
     abort();
   }
 }
@@ -1973,7 +1971,7 @@ void CWriter::visitBinaryOperator(Instruction &I) {
     case Instruction::Shl : Out << " << "; break;
     case Instruction::LShr:
     case Instruction::AShr: Out << " >> "; break;
-    default: std::cerr << "Invalid operator type!" << I; abort();
+    default: cerr << "Invalid operator type!" << I; abort();
     }
 
     writeOperandWithCast(I.getOperand(1), I.getOpcode());
@@ -2099,9 +2097,9 @@ void CWriter::visitCallInst(CallInst &I) {
         Out << ", ";
         // Output the last argument to the enclosing function...
         if (I.getParent()->getParent()->arg_empty()) {
-          std::cerr << "The C backend does not currently support zero "
-                    << "argument varargs functions, such as '"
-                    << I.getParent()->getParent()->getName() << "'!\n";
+          cerr << "The C backend does not currently support zero "
+               << "argument varargs functions, such as '"
+               << I.getParent()->getParent()->getName() << "'!\n";
           abort();
         }
         writeOperand(--I.getParent()->getParent()->arg_end());
diff --git a/lib/Target/CBackend/Writer.cpp b/lib/Target/CBackend/Writer.cpp
index d8fe0e8..7c0d433 100644
--- a/lib/Target/CBackend/Writer.cpp
+++ b/lib/Target/CBackend/Writer.cpp
@@ -42,9 +42,7 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Config/config.h"
 #include <algorithm>
-#include <iostream>
 #include <ios>
-#include <sstream>
 using namespace llvm;
 
 namespace {
@@ -229,7 +227,7 @@ namespace {
     void visitVAArgInst (VAArgInst &I);
 
     void visitInstruction(Instruction &I) {
-      std::cerr << "C Writer does not know about " << I;
+      cerr << "C Writer does not know about " << I;
       abort();
     }
 
@@ -375,7 +373,7 @@ std::ostream &CWriter::printType(std::ostream &Out, const Type *Ty,
     case Type::FloatTyID:  return Out << "float "              << NameSoFar;
     case Type::DoubleTyID: return Out << "double "             << NameSoFar;
     default :
-      std::cerr << "Unknown primitive type: " << *Ty << "\n";
+      cerr << "Unknown primitive type: " << *Ty << "\n";
       abort();
     }
 
@@ -726,8 +724,8 @@ void CWriter::printConstant(Constant *CPV) {
     }
 
     default:
-      std::cerr << "CWriter Error: Unhandled constant expression: "
-                << *CE << "\n";
+      cerr << "CWriter Error: Unhandled constant expression: "
+           << *CE << "\n";
       abort();
     }
   } else if (isa<UndefValue>(CPV) && CPV->getType()->isFirstClassType()) {
@@ -901,7 +899,7 @@ void CWriter::printConstant(Constant *CPV) {
     }
     // FALL THROUGH
   default:
-    std::cerr << "Unknown constant type: " << *CPV << "\n";
+    cerr << "Unknown constant type: " << *CPV << "\n";
     abort();
   }
 }
@@ -1973,7 +1971,7 @@ void CWriter::visitBinaryOperator(Instruction &I) {
     case Instruction::Shl : Out << " << "; break;
     case Instruction::LShr:
     case Instruction::AShr: Out << " >> "; break;
-    default: std::cerr << "Invalid operator type!" << I; abort();
+    default: cerr << "Invalid operator type!" << I; abort();
     }
 
     writeOperandWithCast(I.getOperand(1), I.getOpcode());
@@ -2099,9 +2097,9 @@ void CWriter::visitCallInst(CallInst &I) {
         Out << ", ";
         // Output the last argument to the enclosing function...
         if (I.getParent()->getParent()->arg_empty()) {
-          std::cerr << "The C backend does not currently support zero "
-                    << "argument varargs functions, such as '"
-                    << I.getParent()->getParent()->getName() << "'!\n";
+          cerr << "The C backend does not currently support zero "
+               << "argument varargs functions, such as '"
+               << I.getParent()->getParent()->getName() << "'!\n";
           abort();
         }
         writeOperand(--I.getParent()->getParent()->arg_end());
diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index b2f0f53..6915cbc 100644
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -26,7 +26,6 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Support/Mangler.h"
 #include "llvm/ADT/Statistic.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -308,13 +307,13 @@ bool IA64AsmPrinter::doFinalization(Module &M) {
             SwitchToDataSection(C->isNullValue() ? ".bss" : ".data", I);
             break;
           case GlobalValue::GhostLinkage:
-            std::cerr << "GhostLinkage cannot appear in IA64AsmPrinter!\n";
+            cerr << "GhostLinkage cannot appear in IA64AsmPrinter!\n";
             abort();
           case GlobalValue::DLLImportLinkage:
-            std::cerr << "DLLImport linkage is not supported by this target!\n";
+            cerr << "DLLImport linkage is not supported by this target!\n";
             abort();
           case GlobalValue::DLLExportLinkage:
-            std::cerr << "DLLExport linkage is not supported by this target!\n";
+            cerr << "DLLExport linkage is not supported by this target!\n";
             abort();
           default:
             assert(0 && "Unknown linkage type!");            
diff --git a/lib/Target/IA64/IA64Bundling.cpp b/lib/Target/IA64/IA64Bundling.cpp
index 0c4ae82..9b5e4c7 100644
--- a/lib/Target/IA64/IA64Bundling.cpp
+++ b/lib/Target/IA64/IA64Bundling.cpp
@@ -29,7 +29,6 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/Debug.h"
 #include <set>
-#include <iostream>
 using namespace llvm;
 
 namespace {
diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index 3f2669d..7a49418 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -27,7 +27,6 @@
 #include "llvm/Intrinsics.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
-#include <iostream>
 #include <queue>
 #include <set>
 using namespace llvm;
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index fd9f9ef..3c66c44 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -29,10 +29,8 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
-
 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
   : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
     TII(tii) {}
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 65145e5..032782b 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -41,7 +41,6 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringExtras.h"
-#include <iostream>
 #include <set>
 using namespace llvm;
 
@@ -295,7 +294,7 @@ namespace {
 void PPCAsmPrinter::printOp(const MachineOperand &MO) {
   switch (MO.getType()) {
   case MachineOperand::MO_Immediate:
-    std::cerr << "printOp() does not handle immediate values\n";
+    cerr << "printOp() does not handle immediate values\n";
     abort();
     return;
 
@@ -629,7 +628,7 @@ bool DarwinAsmPrinter::doFinalization(Module &M) {
         SwitchToDataSection("\t.data", I);
         break;
       default:
-        std::cerr << "Unknown linkage type!";
+        cerr << "Unknown linkage type!";
         abort();
       }
 
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 5e5f2cd..7f5e86f 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -24,7 +24,6 @@
 #include "llvm/Support/Debug.h"                   
 #include "llvm/Support/Compiler.h"
 #include "llvm/Target/TargetOptions.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -193,7 +192,7 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
                                                Reloc,
                                                MO.getMachineBasicBlock()));
   } else {
-    std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
+    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
     abort();
   }
 
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 3ca6e4e..69ad1ea 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -16,10 +16,8 @@
 #include "PPC.h"
 #include "PPCInstrInfo.h"
 #include "llvm/Support/Debug.h"
-#include <iostream>
 using namespace llvm;
 
-
 //===----------------------------------------------------------------------===//
 // PowerPC 970 Hazard Recognizer
 //
@@ -52,7 +50,7 @@ PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
 }
 
 void PPCHazardRecognizer970::EndDispatchGroup() {
-  DEBUG(std::cerr << "=== Start of dispatch group\n");
+  DOUT << "=== Start of dispatch group\n";
   NumIssued = 0;
   
   // Structural hazard info.
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1a3508e..d45c255 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -30,7 +30,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Compiler.h"
-#include <iostream>
 #include <queue>
 #include <set>
 using namespace llvm;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index da851e6..1ba701f 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -16,7 +16,6 @@
 #include "PPCGenInstrInfo.inc"
 #include "PPCTargetMachine.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
-#include <iostream>
 using namespace llvm;
 
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
diff --git a/lib/Target/PowerPC/PPCJITInfo.cpp b/lib/Target/PowerPC/PPCJITInfo.cpp
index 14527bf..29fdd6a 100644
--- a/lib/Target/PowerPC/PPCJITInfo.cpp
+++ b/lib/Target/PowerPC/PPCJITInfo.cpp
@@ -18,7 +18,6 @@
 #include "llvm/Config/alloca.h"
 #include "llvm/Support/Debug.h"
 #include <set>
-#include <iostream>
 using namespace llvm;
 
 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 6a21a50..61639c0 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -36,7 +36,6 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
-#include <iostream>
 using namespace llvm;
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.
@@ -77,7 +76,7 @@ unsigned PPCRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
   case R30:  case X30:  case F30:  case V30: return 30;
   case R31:  case X31:  case F31:  case V31: return 31;
   default:
-    std::cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
+    cerr << "Unhandled reg in PPCRegisterInfo::getRegisterNumbering!\n";
     abort();
   }
 }
@@ -234,7 +233,7 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
   } else if (RC == PPC::VRRCRegisterClass) {
     BuildMI(MBB, MI, TII.get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
   } else {
-    std::cerr << "Attempt to copy register that is not GPR or FPR";
+    cerr << "Attempt to copy register that is not GPR or FPR";
     abort();
   }
 }
diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp
index 643acc2..5c18e65 100644
--- a/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -15,7 +15,6 @@
 #include "PPC.h"
 #include "llvm/Module.h"
 #include "PPCGenSubtarget.inc"
-#include <iostream>
 using namespace llvm;
 
 #if defined(__APPLE__)
@@ -80,8 +79,8 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit)
   // If we are generating code for ppc64, verify that options make sense.
   if (is64Bit) {
     if (!has64BitSupport()) {
-      std::cerr << "PPC: Generation of 64-bit code for a 32-bit processor "
-                   "requested.  Ignoring 32-bit processor feature.\n";
+      cerr << "PPC: Generation of 64-bit code for a 32-bit processor "
+           << "requested.  Ignoring 32-bit processor feature.\n";
       Has64BitSupport = true;
     }
     // Silently force 64-bit register use on ppc64.
@@ -91,8 +90,8 @@ PPCSubtarget::PPCSubtarget(const Module &M, const std::string &FS, bool is64Bit)
   // If the user requested use of 64-bit regs, but the cpu selected doesn't
   // support it, warn and ignore.
   if (use64BitRegs() && !has64BitSupport()) {
-    std::cerr << "PPC: 64-bit registers requested on CPU without support.  "
-                 "Disabling 64-bit register use.\n";
+    cerr << "PPC: 64-bit registers requested on CPU without support.  "
+         << "Disabling 64-bit register use.\n";
     Use64BitRegs = false;
   }
   
diff --git a/lib/Target/Sparc/FPMover.cpp b/lib/Target/Sparc/FPMover.cpp
index 2b24d99..b85d2a9 100644
--- a/lib/Target/Sparc/FPMover.cpp
+++ b/lib/Target/Sparc/FPMover.cpp
@@ -19,7 +19,6 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Support/Debug.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -108,12 +107,12 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
         
       MI->getOperand(0).setReg(EvenDestReg);
       MI->getOperand(1).setReg(EvenSrcReg);
-      DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
+      DOUT << "FPMover: the modified instr is: " << *MI;
       // Insert copy for the other half of the double.
       if (DestDReg != SrcDReg) {
         MI = BuildMI(MBB, I, TM.getInstrInfo()->get(SP::FMOVS), OddDestReg)
           .addReg(OddSrcReg);
-        DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
+        DOUT << "FPMover: the inserted instr is: " << *MI;
       }
       ++NumFpDs;
     }
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index 034c8f6..458b153 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -30,7 +30,6 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MathExtras.h"
 #include <cctype>
-#include <iostream>
 using namespace llvm;
 
 namespace {
@@ -266,13 +265,13 @@ bool SparcAsmPrinter::doFinalization(Module &M) {
             SwitchToDataSection(".data", I);
           break;
         case GlobalValue::GhostLinkage:
-          std::cerr << "Should not have any unmaterialized functions!\n";
+          cerr << "Should not have any unmaterialized functions!\n";
           abort();
         case GlobalValue::DLLImportLinkage:
-          std::cerr << "DLLImport linkage is not supported by this target!\n";
+          cerr << "DLLImport linkage is not supported by this target!\n";
           abort();
         case GlobalValue::DLLExportLinkage:
-          std::cerr << "DLLExport linkage is not supported by this target!\n";
+          cerr << "DLLExport linkage is not supported by this target!\n";
           abort();
         default:
           assert(0 && "Unknown linkage type!");          
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 3f3f1e1..e5e9b44 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -24,7 +24,6 @@
 #include "llvm/CodeGen/SSARegMap.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Support/Debug.h"
-#include <iostream>
 #include <queue>
 #include <set>
 using namespace llvm;
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 188fbdc..eee4f6c 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -21,7 +21,6 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Type.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
 using namespace llvm;
 
 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 98912a2..ac43736 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -16,7 +16,6 @@
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
 #include "llvm/Target/TargetMachineRegistry.h"
-#include <iostream>
 using namespace llvm;
 
 namespace {
diff --git a/lib/Target/SubtargetFeature.cpp b/lib/Target/SubtargetFeature.cpp
index de48f4f..8062123 100644
--- a/lib/Target/SubtargetFeature.cpp
+++ b/lib/Target/SubtargetFeature.cpp
@@ -13,10 +13,10 @@
 
 #include "llvm/Target/SubtargetFeature.h"
 #include "llvm/ADT/StringExtras.h"
+#include "llvm/Support/Streams.h"
 #include <algorithm>
 #include <cassert>
 #include <cctype>
-#include <iostream>
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//
@@ -144,23 +144,23 @@ static void Help(const SubtargetFeatureKV *CPUTable, size_t CPUTableSize,
   unsigned MaxFeatLen = getLongestEntryLength(FeatTable, FeatTableSize);
 
   // Print the CPU table.
-  std::cerr << "Available CPUs for this target:\n\n";
+  cerr << "Available CPUs for this target:\n\n";
   for (size_t i = 0; i != CPUTableSize; i++)
-    std::cerr << "  " << CPUTable[i].Key
-              << std::string(MaxCPULen - std::strlen(CPUTable[i].Key), ' ')
-              << " - " << CPUTable[i].Desc << ".\n";
-  std::cerr << "\n";
+    cerr << "  " << CPUTable[i].Key
+         << std::string(MaxCPULen - std::strlen(CPUTable[i].Key), ' ')
+         << " - " << CPUTable[i].Desc << ".\n";
+  cerr << "\n";
   
   // Print the Feature table.
-  std::cerr << "Available features for this target:\n\n";
+  cerr << "Available features for this target:\n\n";
   for (size_t i = 0; i != FeatTableSize; i++)
-    std::cerr << "  " << FeatTable[i].Key
-      << std::string(MaxFeatLen - std::strlen(FeatTable[i].Key), ' ')
-      << " - " << FeatTable[i].Desc << ".\n";
-  std::cerr << "\n";
+    cerr << "  " << FeatTable[i].Key
+         << std::string(MaxFeatLen - std::strlen(FeatTable[i].Key), ' ')
+         << " - " << FeatTable[i].Desc << ".\n";
+  cerr << "\n";
   
-  std::cerr << "Use +feature to enable a feature, or -feature to disable it.\n"
-            << "For example, llc -mcpu=mycpu -mattr=+feature1,-feature2\n";
+  cerr << "Use +feature to enable a feature, or -feature to disable it.\n"
+       << "For example, llc -mcpu=mycpu -mattr=+feature1,-feature2\n";
   exit(1);
 }
 
@@ -231,10 +231,10 @@ uint32_t SubtargetFeatures::getBits(const SubtargetFeatureKV *CPUTable,
     // Set base feature bits
     Bits = CPUEntry->Value;
   } else {
-    std::cerr << "'" << Features[0]
-              << "' is not a recognized processor for this target"
-              << " (ignoring processor)"
-              << "\n";
+    cerr << "'" << Features[0]
+         << "' is not a recognized processor for this target"
+         << " (ignoring processor)"
+         << "\n";
   }
   // Iterate through each feature
   for (size_t i = 1; i < Features.size(); i++) {
@@ -253,10 +253,10 @@ uint32_t SubtargetFeatures::getBits(const SubtargetFeatureKV *CPUTable,
       if (isEnabled(Feature)) Bits |=  FeatureEntry->Value;
       else                    Bits &= ~FeatureEntry->Value;
     } else {
-      std::cerr << "'" << Feature
-                << "' is not a recognized feature for this target"
-                << " (ignoring feature)"
-                << "\n";
+      cerr << "'" << Feature
+           << "' is not a recognized feature for this target"
+           << " (ignoring feature)"
+           << "\n";
     }
   }
   return Bits;
@@ -278,10 +278,10 @@ void *SubtargetFeatures::getInfo(const SubtargetInfoKV *Table,
   if (Entry) {
     return Entry->Value;
   } else {
-    std::cerr << "'" << Features[0]
-              << "' is not a recognized processor for this target"
-              << " (ignoring processor)"
-              << "\n";
+    cerr << "'" << Features[0]
+         << "' is not a recognized processor for this target"
+         << " (ignoring processor)"
+         << "\n";
     return NULL;
   }
 }
@@ -298,5 +298,5 @@ void SubtargetFeatures::print(std::ostream &OS) const {
 /// dump - Dump feature info.
 ///
 void SubtargetFeatures::dump() const {
-  print(std::cerr);
+  print(*cerr.stream());
 }
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 7532127..180e846 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -44,7 +44,6 @@
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/STLExtras.h"
 #include <algorithm>
-#include <iostream>
 #include <set>
 using namespace llvm;
 
@@ -70,12 +69,12 @@ namespace {
     unsigned StackTop;          // The current top of the FP stack.
 
     void dumpStack() const {
-      std::cerr << "Stack contents:";
+      cerr << "Stack contents:";
       for (unsigned i = 0; i != StackTop; ++i) {
-        std::cerr << " FP" << Stack[i];
+        cerr << " FP" << Stack[i];
         assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
       }
-      std::cerr << "\n";
+      cerr << "\n";
     }
   private:
     // getSlot - Return the stack slot number a particular register number is
@@ -211,7 +210,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
         PrevMI = prior(I);
 
     ++NumFP;  // Keep track of # of pseudo instrs
-    DEBUG(std::cerr << "\nFPInst:\t"; MI->print(std::cerr, &(MF.getTarget())));
+    DOUT << "\nFPInst:\t"; MI->print(*cerr.stream(), &(MF.getTarget()));
 
     // Get dead variables list now because the MI pointer may be deleted as part
     // of processing!
@@ -238,7 +237,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
     for (unsigned i = 0, e = DeadRegs.size(); i != e; ++i) {
       unsigned Reg = DeadRegs[i];
       if (Reg >= X86::FP0 && Reg <= X86::FP6) {
-        DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
+        DOUT << "Register FP#" << Reg-X86::FP0 << " is dead!\n";
         freeStackSlotAfter(I, Reg-X86::FP0);
       }
     }
@@ -247,13 +246,13 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
     DEBUG(
       MachineBasicBlock::iterator PrevI(PrevMI);
       if (I == PrevI) {
-        std::cerr << "Just deleted pseudo instruction\n";
+        cerr << "Just deleted pseudo instruction\n";
       } else {
         MachineBasicBlock::iterator Start = I;
         // Rewind to first instruction newly inserted.
         while (Start != BB.begin() && prior(Start) != PrevI) --Start;
-        std::cerr << "Inserted instructions:\n\t";
-        Start->print(std::cerr, &MF.getTarget());
+        cerr << "Inserted instructions:\n\t";
+        Start->print(*cerr.stream(), &MF.getTarget());
         while (++Start != next(I));
       }
       dumpStack();
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 4f84327..5c0bd28 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -34,7 +34,6 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/ADT/Statistic.h"
-#include <iostream>
 #include <queue>
 #include <set>
 using namespace llvm;
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 86b2563..3c882ea 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -32,8 +32,6 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/STLExtras.h"
-#include <iostream>
-
 using namespace llvm;
 
 namespace {
@@ -244,8 +242,8 @@ namespace {
 static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
   for (unsigned i = 1; i != NumEntries; ++i)
     if (!(Table[i-1] < Table[i])) {
-      std::cerr << "Entries out of order " << Table[i-1].from
-                << " " << Table[i].from << "\n";
+      cerr << "Entries out of order " << Table[i-1].from
+           << " " << Table[i].from << "\n";
       return false;
     }
   return true;
@@ -845,8 +843,8 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr *MI,
   
   // No fusion 
   if (PrintFailedFusing)
-    std::cerr << "We failed to fuse ("
-              << ((i == 1) ? "r" : "s") << "): " << *MI;
+    cerr << "We failed to fuse ("
+         << ((i == 1) ? "r" : "s") << "): " << *MI;
   return NULL;
 }
 
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index 2459ed1..ff88fdb 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -15,7 +15,6 @@
 #include "X86GenSubtarget.inc"
 #include "llvm/Module.h"
 #include "llvm/Support/CommandLine.h"
-#include <iostream>
 using namespace llvm;
 
 cl::opt<X86Subtarget::AsmWriterFlavorTy>
@@ -224,10 +223,10 @@ X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
     ParseSubtargetFeatures(FS, CPU);
     
     if (Is64Bit && !HasX86_64)
-      std::cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
-                   "requested.\n";
+      cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
+           << "requested.\n";
     if (Is64Bit && X86SSELevel < SSE2)
-      std::cerr << "Warning: 64-bit processors all have at least SSE2.\n";
+      cerr << "Warning: 64-bit processors all have at least SSE2.\n";
   } else {
     // Otherwise, use CPUID to auto-detect feature set.
     AutoDetectSubtargetFeatures();