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| author | Chris Lattner <sabre@nondot.org> | 2004-04-07 04:05:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-04-07 04:05:49 +0000 |
| commit | f97b31e9cfb528e56603b123eb2a5426b400bd96 (patch) | |
| tree | a6ddb0e9d917dcde511c68940bf9010c18a91194 /lib/Target | |
| parent | 0f51cc1759e2162485b5f9ee57b3b5bc8f5c6759 (diff) | |
| download | external_llvm-f97b31e9cfb528e56603b123eb2a5426b400bd96.zip external_llvm-f97b31e9cfb528e56603b123eb2a5426b400bd96.tar.gz external_llvm-f97b31e9cfb528e56603b123eb2a5426b400bd96.tar.bz2 | |
Merge my changes with brians
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12736 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 11 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8RegisterInfo.td | 11 |
2 files changed, 10 insertions, 12 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index 6d2496d..ca0bcdc 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -24,16 +24,12 @@ class Rf<bits<5> num> : Register { class Rd<bits<5> num> : Register { field bits<5> Num = num; } -// Rs - Special "ancillary state registers" +// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR, +// WIM, TBR, etc registers class Rs<bits<5> num> : Register { field bits<5> Num = num; } -// Special register used for multiplies and divides -let Namespace = "V8" in { - def Y : Rs<0>; -} - let Namespace = "V8" in { def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; @@ -62,6 +58,9 @@ let Namespace = "V8" in { def D4 : Rd< 8>; def D5 : Rd<10>; def D6 : Rd<12>; def D7 : Rd<14>; def D8 : Rd<16>; def D9 : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>; def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>; + + // The Y register. + def Y : Rs<0>; } diff --git a/lib/Target/SparcV8/SparcV8RegisterInfo.td b/lib/Target/SparcV8/SparcV8RegisterInfo.td index 6d2496d..ca0bcdc 100644 --- a/lib/Target/SparcV8/SparcV8RegisterInfo.td +++ b/lib/Target/SparcV8/SparcV8RegisterInfo.td @@ -24,16 +24,12 @@ class Rf<bits<5> num> : Register { class Rd<bits<5> num> : Register { field bits<5> Num = num; } -// Rs - Special "ancillary state registers" +// Rs - Special "ancillary state registers" registers, like the Y, ASR, PSR, +// WIM, TBR, etc registers class Rs<bits<5> num> : Register { field bits<5> Num = num; } -// Special register used for multiplies and divides -let Namespace = "V8" in { - def Y : Rs<0>; -} - let Namespace = "V8" in { def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>; def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>; @@ -62,6 +58,9 @@ let Namespace = "V8" in { def D4 : Rd< 8>; def D5 : Rd<10>; def D6 : Rd<12>; def D7 : Rd<14>; def D8 : Rd<16>; def D9 : Rd<18>; def D10 : Rd<20>; def D11 : Rd<22>; def D12 : Rd<24>; def D13 : Rd<26>; def D14 : Rd<28>; def D15 : Rd<30>; + + // The Y register. + def Y : Rs<0>; } |