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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-03 13:02:22 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-03 13:02:22 +0000 |
| commit | fff5f76c46b345638dc553cd598d8222d61ea423 (patch) | |
| tree | eace7f8a950f493294bb4886704a671ff88a9396 /lib/Target | |
| parent | 1df221f2bb8e8380e255d1bec73ab07b388d01a2 (diff) | |
| download | external_llvm-fff5f76c46b345638dc553cd598d8222d61ea423.zip external_llvm-fff5f76c46b345638dc553cd598d8222d61ea423.tar.gz external_llvm-fff5f76c46b345638dc553cd598d8222d61ea423.tar.bz2 | |
gas uses lower letter for register names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70711 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/MSP430/MSP430RegisterInfo.td | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index fd78161..cc17e32 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -20,22 +20,22 @@ class MSP430Reg<bits<4> num, string n> : Register<n> { // Registers //===----------------------------------------------------------------------===// -def PC : MSP430Reg<0, "R0">; -def SP : MSP430Reg<1, "R1">; -def SR : MSP430Reg<2, "R2">; -def CG : MSP430Reg<3, "R3">; -def FP : MSP430Reg<4, "R4">; -def R5 : MSP430Reg<5, "R5">; -def R6 : MSP430Reg<6, "R6">; -def R7 : MSP430Reg<7, "R7">; -def R8 : MSP430Reg<8, "R8">; -def R9 : MSP430Reg<9, "R9">; -def R10 : MSP430Reg<10, "R10">; -def R11 : MSP430Reg<11, "R11">; -def R12 : MSP430Reg<12, "R12">; -def R13 : MSP430Reg<13, "R13">; -def R14 : MSP430Reg<14, "R14">; -def R15 : MSP430Reg<15, "R15">; +def PC : MSP430Reg<0, "r0">; +def SP : MSP430Reg<1, "r1">; +def SR : MSP430Reg<2, "r2">; +def CG : MSP430Reg<3, "r3">; +def FP : MSP430Reg<4, "r4">; +def R5 : MSP430Reg<5, "r5">; +def R6 : MSP430Reg<6, "r6">; +def R7 : MSP430Reg<7, "r7">; +def R8 : MSP430Reg<8, "r8">; +def R9 : MSP430Reg<9, "r9">; +def R10 : MSP430Reg<10, "r10">; +def R11 : MSP430Reg<11, "r11">; +def R12 : MSP430Reg<12, "r12">; +def R13 : MSP430Reg<13, "r13">; +def R14 : MSP430Reg<14, "r14">; +def R15 : MSP430Reg<15, "r15">; // FIXME: we need subregs & special handling for 8 bit stuff |