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authorChris Lattner <sabre@nondot.org>2006-11-27 19:55:07 +0000
committerChris Lattner <sabre@nondot.org>2006-11-27 19:55:07 +0000
commitf2f1643037d8631ec3ddce8a1a131493e5bcd8b6 (patch)
tree21ae9df19a2ddfd731247a08d4d18524dc3c940d /lib/Transforms
parente434f4ac50aea8da7b73c00c988599a04ec739d0 (diff)
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Fix PR1014 and InstCombine/2006-11-27-XorBug.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31941 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms')
-rw-r--r--lib/Transforms/Scalar/InstructionCombining.cpp18
1 files changed, 8 insertions, 10 deletions
diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index a13b7e7..2236240 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -939,17 +939,15 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, uint64_t DemandedMask,
// Output known-1 are known to be set if set in only one of the LHS, RHS.
uint64_t KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
- // If all of the unknown bits are known to be zero on one side or the other
- // (but not both) turn this into an *inclusive* or.
+ // If all of the demanded bits are known to be zero on one side or the
+ // other, turn this into an *inclusive* or.
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
- if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut)) {
- if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits) {
- Instruction *Or =
- BinaryOperator::createOr(I->getOperand(0), I->getOperand(1),
- I->getName());
- InsertNewInstBefore(Or, *I);
- return UpdateValueUsesWith(I, Or);
- }
+ if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0) {
+ Instruction *Or =
+ BinaryOperator::createOr(I->getOperand(0), I->getOperand(1),
+ I->getName());
+ InsertNewInstBefore(Or, *I);
+ return UpdateValueUsesWith(I, Or);
}
// If all of the demanded bits on one side are known, and all of the set