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author | Chris Lattner <sabre@nondot.org> | 2009-10-28 00:19:10 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2009-10-28 00:19:10 +0000 |
commit | 4c3800f0172e2fdc0b3b2e78dbaf89b150f4e04f (patch) | |
tree | 48dc361e1986e6e489f48619e73e609adb7c716a /lib/VMCore | |
parent | 746f7fd8f0fa1d3d83dc28ddfc3be561dcf09deb (diff) | |
download | external_llvm-4c3800f0172e2fdc0b3b2e78dbaf89b150f4e04f.zip external_llvm-4c3800f0172e2fdc0b3b2e78dbaf89b150f4e04f.tar.gz external_llvm-4c3800f0172e2fdc0b3b2e78dbaf89b150f4e04f.tar.bz2 |
rename indbr -> indirectbr to appease the residents of #llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85351 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/VMCore')
-rw-r--r-- | lib/VMCore/AsmWriter.cpp | 4 | ||||
-rw-r--r-- | lib/VMCore/Instruction.cpp | 2 | ||||
-rw-r--r-- | lib/VMCore/Instructions.cpp | 37 |
3 files changed, 22 insertions, 21 deletions
diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp index 5a92432..296cc25 100644 --- a/lib/VMCore/AsmWriter.cpp +++ b/lib/VMCore/AsmWriter.cpp @@ -1846,8 +1846,8 @@ void AssemblyWriter::printInstruction(const Instruction &I) { writeOperand(I.getOperand(op+1), true); } Out << "\n ]"; - } else if (isa<IndBrInst>(I)) { - // Special case indbr instruction to get formatting nice and correct. + } else if (isa<IndirectBrInst>(I)) { + // Special case indirectbr instruction to get formatting nice and correct. Out << ' '; writeOperand(Operand, true); Out << ", "; diff --git a/lib/VMCore/Instruction.cpp b/lib/VMCore/Instruction.cpp index c48e75c..879c073 100644 --- a/lib/VMCore/Instruction.cpp +++ b/lib/VMCore/Instruction.cpp @@ -103,7 +103,7 @@ const char *Instruction::getOpcodeName(unsigned OpCode) { case Ret: return "ret"; case Br: return "br"; case Switch: return "switch"; - case IndBr: return "indbr"; + case IndirectBr: return "indirectbr"; case Invoke: return "invoke"; case Unwind: return "unwind"; case Unreachable: return "unreachable"; diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp index 5a6d376..1e63436 100644 --- a/lib/VMCore/Instructions.cpp +++ b/lib/VMCore/Instructions.cpp @@ -3090,7 +3090,7 @@ void SwitchInst::setSuccessorV(unsigned idx, BasicBlock *B) { // SwitchInst Implementation //===----------------------------------------------------------------------===// -void IndBrInst::init(Value *Address, unsigned NumDests) { +void IndirectBrInst::init(Value *Address, unsigned NumDests) { assert(Address); ReservedSpace = 1+NumDests; NumOperands = 1; @@ -3107,7 +3107,7 @@ void IndBrInst::init(Value *Address, unsigned NumDests) { /// 2. If NumOps > NumOperands, reserve space for NumOps operands. /// 3. If NumOps == NumOperands, trim the reserved space. /// -void IndBrInst::resizeOperands(unsigned NumOps) { +void IndirectBrInst::resizeOperands(unsigned NumOps) { unsigned e = getNumOperands(); if (NumOps == 0) { NumOps = e*2; @@ -3129,21 +3129,22 @@ void IndBrInst::resizeOperands(unsigned NumOps) { if (OldOps) Use::zap(OldOps, OldOps + e, true); } -IndBrInst::IndBrInst(Value *Address, unsigned NumCases, - Instruction *InsertBefore) -: TerminatorInst(Type::getVoidTy(Address->getContext()), Instruction::IndBr, +IndirectBrInst::IndirectBrInst(Value *Address, unsigned NumCases, + Instruction *InsertBefore) +: TerminatorInst(Type::getVoidTy(Address->getContext()),Instruction::IndirectBr, 0, 0, InsertBefore) { init(Address, NumCases); } -IndBrInst::IndBrInst(Value *Address, unsigned NumCases, BasicBlock *InsertAtEnd) -: TerminatorInst(Type::getVoidTy(Address->getContext()), Instruction::IndBr, +IndirectBrInst::IndirectBrInst(Value *Address, unsigned NumCases, + BasicBlock *InsertAtEnd) +: TerminatorInst(Type::getVoidTy(Address->getContext()),Instruction::IndirectBr, 0, 0, InsertAtEnd) { init(Address, NumCases); } -IndBrInst::IndBrInst(const IndBrInst &IBI) - : TerminatorInst(Type::getVoidTy(IBI.getContext()), Instruction::IndBr, +IndirectBrInst::IndirectBrInst(const IndirectBrInst &IBI) + : TerminatorInst(Type::getVoidTy(IBI.getContext()), Instruction::IndirectBr, allocHungoffUses(IBI.getNumOperands()), IBI.getNumOperands()) { Use *OL = OperandList, *InOL = IBI.OperandList; @@ -3152,13 +3153,13 @@ IndBrInst::IndBrInst(const IndBrInst &IBI) SubclassOptionalData = IBI.SubclassOptionalData; } -IndBrInst::~IndBrInst() { +IndirectBrInst::~IndirectBrInst() { dropHungoffUses(OperandList); } /// addDestination - Add a destination. /// -void IndBrInst::addDestination(BasicBlock *DestBB) { +void IndirectBrInst::addDestination(BasicBlock *DestBB) { unsigned OpNo = NumOperands; if (OpNo+1 > ReservedSpace) resizeOperands(0); // Get more space! @@ -3169,8 +3170,8 @@ void IndBrInst::addDestination(BasicBlock *DestBB) { } /// removeDestination - This method removes the specified successor from the -/// indbr instruction. -void IndBrInst::removeDestination(unsigned idx) { +/// indirectbr instruction. +void IndirectBrInst::removeDestination(unsigned idx) { assert(idx < getNumOperands()-1 && "Successor index out of range!"); unsigned NumOps = getNumOperands(); @@ -3184,13 +3185,13 @@ void IndBrInst::removeDestination(unsigned idx) { NumOperands = NumOps-1; } -BasicBlock *IndBrInst::getSuccessorV(unsigned idx) const { +BasicBlock *IndirectBrInst::getSuccessorV(unsigned idx) const { return getSuccessor(idx); } -unsigned IndBrInst::getNumSuccessorsV() const { +unsigned IndirectBrInst::getNumSuccessorsV() const { return getNumSuccessors(); } -void IndBrInst::setSuccessorV(unsigned idx, BasicBlock *B) { +void IndirectBrInst::setSuccessorV(unsigned idx, BasicBlock *B) { setSuccessor(idx, B); } @@ -3335,8 +3336,8 @@ SwitchInst *SwitchInst::clone_impl() const { return new SwitchInst(*this); } -IndBrInst *IndBrInst::clone_impl() const { - return new IndBrInst(*this); +IndirectBrInst *IndirectBrInst::clone_impl() const { + return new IndirectBrInst(*this); } |