silence warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31397 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 0 insertions, 50 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 7befa9c..b37d282 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -155,41 +155,6 @@ void ScheduleDAGRRList::CommuteNodesToReducePressure() {
 //  Bottom-Up Scheduling
 //===----------------------------------------------------------------------===//
 
-static const TargetRegisterClass *getRegClass(SUnit *SU,
-                                              const TargetInstrInfo *TII,
-                                              const MRegisterInfo *MRI,
-                                              SSARegMap *RegMap) {
-  if (SU->Node->isTargetOpcode()) {
-    unsigned Opc = SU->Node->getTargetOpcode();
-    const TargetInstrDescriptor &II = TII->get(Opc);
-    return MRI->getRegClass(II.OpInfo->RegClass);
-  } else {
-    assert(SU->Node->getOpcode() == ISD::CopyFromReg);
-    unsigned SrcReg = cast<RegisterSDNode>(SU->Node->getOperand(1))->getReg();
-    if (MRegisterInfo::isVirtualRegister(SrcReg))
-      return RegMap->getRegClass(SrcReg);
-    else {
-      for (MRegisterInfo::regclass_iterator I = MRI->regclass_begin(),
-             E = MRI->regclass_end(); I != E; ++I)
-        if ((*I)->hasType(SU->Node->getValueType(0)) &&
-            (*I)->contains(SrcReg))
-          return *I;
-      assert(false && "Couldn't find register class for reg copy!");
-    }
-    return NULL;
-  }
-}
-
-static unsigned getNumResults(SUnit *SU) {
-  unsigned NumResults = 0;
-  for (unsigned i = 0, e = SU->Node->getNumValues(); i != e; ++i) {
-    MVT::ValueType VT = SU->Node->getValueType(i);
-    if (VT != MVT::Other && VT != MVT::Flag)
-      NumResults++;
-  }
-  return NumResults;
-}
-
 /// ReleasePred - Decrement the NumSuccsLeft count of a predecessor. Add it to
 /// the Available queue is the count reaches zero. Also update its cycle bound.
 void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain, 
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index bfd9a80..c2ee956 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -39,15 +39,6 @@ static SDVTList makeVTList(const MVT::ValueType *VTs, unsigned NumVTs) {
   return Res;
 }
 
-// isInvertibleForFree - Return true if there is no cost to emitting the logical
-// inverse of this node.
-static bool isInvertibleForFree(SDOperand N) {
-  if (isa<ConstantSDNode>(N.Val)) return true;
-  if (N.Val->getOpcode() == ISD::SETCC && N.Val->hasOneUse())
-    return true;
-  return false;
-}
-
 //===----------------------------------------------------------------------===//
 //                              ConstantFPSDNode Class
 //===----------------------------------------------------------------------===//
@@ -255,12 +246,6 @@ const TargetMachine &SelectionDAG::getTarget() const {
 //                           SDNode Profile Support
 //===----------------------------------------------------------------------===//
 
-/// getNodeIDOpcode - Return the opcode that has been set for this NodeID.
-///
-static unsigned getNodeIDOpcode(FoldingSetNodeID &ID)  {
-  return ID.getRawData(0);
-}
-
 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
 ///
 static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)  {