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authorDuncan Sands <baldrick@free.fr>2009-01-28 14:42:54 +0000
committerDuncan Sands <baldrick@free.fr>2009-01-28 14:42:54 +0000
commit0b3aa26384ff37597f1d686a834252f97a619380 (patch)
tree49b5d20c406f67c9ff7313cc70ff5e2f5cbc1e9a /lib
parent1465d61bdd36cfd6021036a527895f0dd358e97d (diff)
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Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63199 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp13
1 files changed, 5 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 982177c..b543b9e 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -374,12 +374,9 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
/// larger then ValueVT then AssertOp can be used to specify whether the extra
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
/// (ISD::AssertSext).
-static SDValue getCopyFromParts(SelectionDAG &DAG,
- const SDValue *Parts,
- unsigned NumParts,
- MVT PartVT,
- MVT ValueVT,
- ISD::NodeType AssertOp = ISD::DELETED_NODE) {
+static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts,
+ unsigned NumParts, MVT PartVT, MVT ValueVT,
+ ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
SDValue Val = Parts[0];
@@ -587,8 +584,8 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val,
unsigned RoundBits = RoundParts * PartBits;
unsigned OddParts = NumParts - RoundParts;
SDValue OddVal = DAG.getNode(ISD::SRL, ValueVT, Val,
- DAG.getConstant(RoundBits,
- TLI.getShiftAmountTy()));
+ DAG.getConstant(RoundBits,
+ TLI.getShiftAmountTy()));
getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT);
if (TLI.isBigEndian())
// The odd parts were reversed by getCopyToParts - unreverse them.