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| author | Evan Cheng <evan.cheng@apple.com> | 2010-12-14 03:22:07 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-12-14 03:22:07 +0000 |
| commit | 0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef (patch) | |
| tree | a346697018de0bd5a92cfb7166ec96eafeb60418 /lib | |
| parent | db934e747485cc9b4378a02c6d6a47fc83657996 (diff) | |
| download | external_llvm-0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef.zip external_llvm-0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef.tar.gz external_llvm-0c1aec18911f2a67fb37b6593d08f4f8cb7e18ef.tar.bz2 | |
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 3af04f1..5fbc5f8 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -4809,6 +4809,25 @@ static SDValue PerformORCombine(SDNode *N, return SDValue(); } +/// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff +/// C1 & C2 == C1. +static SDValue PerformBFICombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI) { + SDValue N1 = N->getOperand(1); + if (N1.getOpcode() == ISD::AND) { + ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); + if (!N11C) + return SDValue(); + unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); + unsigned Mask2 = N11C->getZExtValue(); + if ((Mask & Mask2) == Mask2) + return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), + N->getOperand(0), N1.getOperand(0), + N->getOperand(2)); + } + return SDValue(); +} + /// PerformVMOVRRDCombine - Target-specific dag combine xforms for /// ARMISD::VMOVRRD. static SDValue PerformVMOVRRDCombine(SDNode *N, @@ -5398,6 +5417,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); case ISD::OR: return PerformORCombine(N, DCI, Subtarget); case ISD::AND: return PerformANDCombine(N, DCI); + case ARMISD::BFI: return PerformBFICombine(N, DCI); case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG); |