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| author | David Majnemer <david.majnemer@gmail.com> | 2013-09-26 04:11:24 +0000 |
|---|---|---|
| committer | David Majnemer <david.majnemer@gmail.com> | 2013-09-26 04:11:24 +0000 |
| commit | 11c2b15c0a8282cfdc1c74968ebaba92f1fdae34 (patch) | |
| tree | 9cfd8250b62ec739445273e7f3e8970216ab22e0 /lib | |
| parent | 9fa81ab83898314d1a6608e8303dc57253292796 (diff) | |
| download | external_llvm-11c2b15c0a8282cfdc1c74968ebaba92f1fdae34.zip external_llvm-11c2b15c0a8282cfdc1c74968ebaba92f1fdae34.tar.gz external_llvm-11c2b15c0a8282cfdc1c74968ebaba92f1fdae34.tar.bz2 | |
PPC: Add support for fctid and fctiw
Encodings were checked against the Power ISA documents and double
checked against binutils.
This fixes PR17350.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191419 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.h | 8 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 3 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 5 |
3 files changed, 12 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index df3af35..b988199 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -42,10 +42,10 @@ namespace llvm { /// unsigned integers and single-precision outputs. FCFIDU, FCFIDS, FCFIDUS, - /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 - /// operand, producing an f64 value containing the integer representation - /// of that FP value. - FCTIDZ, FCTIWZ, + /// FCTI[D,W]Z? - The FCTID, FCTIDZ, FCTIW and FCTIWZ instructions, + /// taking an f32 or f64 operand, producing an f64 value containing the + /// integer representation of that FP value. + FCTID, FCTIDZ, FCTIW, FCTIWZ, /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for /// unsigned integers. diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index c9e70c8..6025afb 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -968,6 +968,9 @@ let PPC970_Unit = 3, neverHasSideEffects = 1, defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), "fcfid", "$frD, $frB", FPGeneral, [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; +defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), + "fctid", "$frD, $frB", FPGeneral, + [(set f64:$frD, (PPCfctid f64:$frB))]>, isPPC64; defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), "fctidz", "$frD, $frB", FPGeneral, [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index a9c916f..9baa791 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -69,7 +69,9 @@ def PPCfcfid : SDNode<"PPCISD::FCFID", SDTFPUnaryOp, []>; def PPCfcfidu : SDNode<"PPCISD::FCFIDU", SDTFPUnaryOp, []>; def PPCfcfids : SDNode<"PPCISD::FCFIDS", SDTFPRoundOp, []>; def PPCfcfidus: SDNode<"PPCISD::FCFIDUS", SDTFPRoundOp, []>; +def PPCfctid : SDNode<"PPCISD::FCTID", SDTFPUnaryOp, []>; def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>; +def PPCfctiw : SDNode<"PPCISD::FCTIW", SDTFPUnaryOp, []>; def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>; def PPCfctiduz: SDNode<"PPCISD::FCTIDUZ",SDTFPUnaryOp, []>; def PPCfctiwuz: SDNode<"PPCISD::FCTIWUZ",SDTFPUnaryOp, []>; @@ -1692,6 +1694,9 @@ let isCompare = 1, neverHasSideEffects = 1 in { let Uses = [RM] in { let neverHasSideEffects = 1 in { + defm FCTIW : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB), + "fctiw", "$frD, $frB", FPGeneral, + [(set f64:$frD, (PPCfctiw f64:$frB))]>; defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB), "fctiwz", "$frD, $frB", FPGeneral, [(set f64:$frD, (PPCfctiwz f64:$frB))]>; |