diff options
author | Duncan Sands <baldrick@free.fr> | 2009-01-21 09:00:29 +0000 |
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committer | Duncan Sands <baldrick@free.fr> | 2009-01-21 09:00:29 +0000 |
commit | 1497b52861fa267815ae822ce247ca74746ef211 (patch) | |
tree | d57e9c6df9132b004dacd529f2e4549f955d2cf1 /lib | |
parent | 41cb4919733565c697e529494f3fcfa380f318bb (diff) | |
download | external_llvm-1497b52861fa267815ae822ce247ca74746ef211.zip external_llvm-1497b52861fa267815ae822ce247ca74746ef211.tar.gz external_llvm-1497b52861fa267815ae822ce247ca74746ef211.tar.bz2 |
Cleanup whitespace and comments, and tweak some
prototypes, in operand type legalization. No
functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62680 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 84 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.cpp | 14 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeTypes.h | 2 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 9 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.cpp | 14 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.h | 6 |
7 files changed, 64 insertions, 67 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index aae84de..8379551 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -722,7 +722,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { Lo = Hi = SDValue(); // See if the target wants to custom expand this node. - if (CustomLowerResults(N, ResNo, true)) + if (CustomLowerResults(N, N->getValueType(ResNo), true)) return; switch (N->getOpcode()) { diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 89ae2fd..b5b249a 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -31,10 +31,10 @@ using namespace llvm; /// expansion, we just know that (at least) one result needs promotion. void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n"); - SDValue Result = SDValue(); + SDValue Res = SDValue(); // See if the target wants to custom expand this node. - if (CustomLowerResults(N, ResNo, true)) + if (CustomLowerResults(N, N->getValueType(ResNo), true)) return; switch (N->getOpcode()) { @@ -45,58 +45,58 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { #endif assert(0 && "Do not know how to promote this operator!"); abort(); - case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break; - case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break; - case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break; - case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break; - case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break; - case ISD::Constant: Result = PromoteIntRes_Constant(N); break; + case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; + case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; + case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break; + case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; + case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; + case ISD::Constant: Res = PromoteIntRes_Constant(N); break; case ISD::CONVERT_RNDSAT: - Result = PromoteIntRes_CONVERT_RNDSAT(N); break; - case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break; - case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break; - case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break; + Res = PromoteIntRes_CONVERT_RNDSAT(N); break; + case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; + case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break; + case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; case ISD::EXTRACT_VECTOR_ELT: - Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; - case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; - case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break; - case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break; - case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break; - case ISD::SHL: Result = PromoteIntRes_SHL(N); break; + Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break; + case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break; + case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break; + case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break; + case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break; + case ISD::SHL: Res = PromoteIntRes_SHL(N); break; case ISD::SIGN_EXTEND_INREG: - Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break; - case ISD::SRA: Result = PromoteIntRes_SRA(N); break; - case ISD::SRL: Result = PromoteIntRes_SRL(N); break; - case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break; - case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break; - case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break; + Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break; + case ISD::SRA: Res = PromoteIntRes_SRA(N); break; + case ISD::SRL: Res = PromoteIntRes_SRL(N); break; + case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break; + case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break; + case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break; case ISD::SIGN_EXTEND: case ISD::ZERO_EXTEND: - case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break; + case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; case ISD::FP_TO_SINT: - case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break; + case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break; case ISD::AND: case ISD::OR: case ISD::XOR: case ISD::ADD: case ISD::SUB: - case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break; + case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break; case ISD::SDIV: - case ISD::SREM: Result = PromoteIntRes_SDIV(N); break; + case ISD::SREM: Res = PromoteIntRes_SDIV(N); break; case ISD::UDIV: - case ISD::UREM: Result = PromoteIntRes_UDIV(N); break; + case ISD::UREM: Res = PromoteIntRes_UDIV(N); break; case ISD::SADDO: - case ISD::SSUBO: Result = PromoteIntRes_SADDSUBO(N, ResNo); break; + case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; case ISD::UADDO: - case ISD::USUBO: Result = PromoteIntRes_UADDSUBO(N, ResNo); break; + case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; case ISD::SMULO: - case ISD::UMULO: Result = PromoteIntRes_XMULO(N, ResNo); break; + case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; case ISD::ATOMIC_LOAD_ADD: case ISD::ATOMIC_LOAD_SUB: @@ -109,15 +109,15 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { case ISD::ATOMIC_LOAD_UMIN: case ISD::ATOMIC_LOAD_UMAX: case ISD::ATOMIC_SWAP: - Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; + Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break; case ISD::ATOMIC_CMP_SWAP: - Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; + Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break; } - // If Result is null, the sub-method took care of registering the result. - if (Result.getNode()) - SetPromotedInteger(SDValue(N, ResNo), Result); + // If the result is null then the sub-method took care of registering it. + if (Res.getNode()) + SetPromotedInteger(SDValue(N, ResNo), Res); } SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) { @@ -623,7 +623,7 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n"); SDValue Res = SDValue(); - if (CustomLowerResults(N, OpNo, false)) + if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) return false; switch (N->getOpcode()) { @@ -656,9 +656,9 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) { case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break; case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; } - + // If the result is null, the sub-method took care of registering results etc. - if (! Res.getNode()) return false; + if (!Res.getNode()) return false; // If the result is N, the sub-method updated N in place. Tell the legalizer // core about this. @@ -918,7 +918,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) { Lo = Hi = SDValue(); // See if the target wants to custom expand this node. - if (CustomLowerResults(N, ResNo, true)) + if (CustomLowerResults(N, N->getValueType(ResNo), true)) return; switch (N->getOpcode()) { @@ -1848,7 +1848,7 @@ bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) { DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n"); SDValue Res = SDValue(); - if (CustomLowerResults(N, OpNo, false)) + if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false)) return false; switch (N->getOpcode()) { diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index ff7b8a9..a4f3917 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -848,27 +848,23 @@ SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op, /// CustomLowerResults - Replace the node's results with custom code provided /// by the target and return "true", or do nothing and return "false". -/// The last parameter is FALSE if we are dealing with a node with legal +/// The last parameter is FALSE if we are dealing with a node with legal /// result types and illegal operand. The second parameter denotes the illegal /// OperandNo in that case. /// The last parameter being TRUE means we are dealing with a -/// node with illegal result types. The second parameter denotes the illegal +/// node with illegal result types. The second parameter denotes the illegal /// ResNo in that case. -bool DAGTypeLegalizer::CustomLowerResults(SDNode *N, unsigned Num, +bool DAGTypeLegalizer::CustomLowerResults(SDNode *N, MVT VT, bool LegalizeResult) { - // Get the type of illegal Result or Operand. - MVT ValueTy = (LegalizeResult) ? N->getValueType(Num) - : N->getOperand(Num).getValueType(); - // See if the target wants to custom lower this node. - if (TLI.getOperationAction(N->getOpcode(), ValueTy) != TargetLowering::Custom) + if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom) return false; SmallVector<SDValue, 8> Results; if (LegalizeResult) TLI.ReplaceNodeResults(N, Results, DAG); else - TLI.LowerOperationWrapper(SDValue(N, 0), Results, DAG); + TLI.LowerOperationWrapper(N, Results, DAG); if (Results.empty()) // The target didn't want to custom lower it after all. diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index d57aec0..a2c91cb 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -191,7 +191,7 @@ private: // Common routines. SDValue BitConvertToInteger(SDValue Op); SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT); - bool CustomLowerResults(SDNode *N, unsigned ResNo, bool LegalizeResult); + bool CustomLowerResults(SDNode *N, MVT VT, bool LegalizeResult); SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index); SDValue JoinIntegers(SDValue Lo, SDValue Hi); SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index d0023a0..f971069 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -5568,11 +5568,10 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, return std::make_pair(Res, Chain); } -void TargetLowering::LowerOperationWrapper(SDValue Op, - SmallVectorImpl<SDValue> &Results, - SelectionDAG &DAG) { - SDValue Res; - Res = LowerOperation(Op, DAG); +void TargetLowering::LowerOperationWrapper(SDNode *N, + SmallVectorImpl<SDValue> &Results, + SelectionDAG &DAG) { + SDValue Res = LowerOperation(SDValue(N, 0), DAG); if (Res.getNode()) Results.push_back(Res); } diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index 72f073a..ae031bc 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -762,9 +762,11 @@ SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { return Call; } -void PIC16TargetLowering::LowerOperationWrapper(SDValue Op, - SmallVectorImpl<SDValue>&Results, - SelectionDAG &DAG) { +void +PIC16TargetLowering::LowerOperationWrapper(SDNode *N, + SmallVectorImpl<SDValue>&Results, + SelectionDAG &DAG) { + SDValue Op = SDValue(N, 0); SDValue Res; unsigned i; switch (Op.getOpcode()) { @@ -783,12 +785,12 @@ void PIC16TargetLowering::LowerOperationWrapper(SDValue Op, return; } } - SDNode *N = Res.getNode(); + + N = Res.getNode(); unsigned NumValues = N->getNumValues(); - for (i=0; i< NumValues ; i++) { + for (i = 0; i < NumValues ; i++) { Results.push_back(SDValue(N, i)); } - } SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index 73cebeb..78571f4 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -97,9 +97,9 @@ namespace llvm { virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG); - virtual void LowerOperationWrapper(SDValue Op, - SmallVectorImpl<SDValue> &Results, - SelectionDAG &DAG); + virtual void LowerOperationWrapper(SDNode *N, + SmallVectorImpl<SDValue> &Results, + SelectionDAG &DAG); SDValue ExpandStore(SDNode *N, SelectionDAG &DAG); SDValue ExpandLoad(SDNode *N, SelectionDAG &DAG); |