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author | Evan Cheng <evan.cheng@apple.com> | 2010-10-08 18:42:25 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-08 18:42:25 +0000 |
commit | 1aca5bc1353d4e2c7706149efbc5393aa9e2cc3f (patch) | |
tree | 23b5f5ddf5f8b4f862dc5a44b5984eafc9b88e26 /lib | |
parent | 95b4672234aa4745722fe5cb04f7bb6670faca72 (diff) | |
download | external_llvm-1aca5bc1353d4e2c7706149efbc5393aa9e2cc3f.zip external_llvm-1aca5bc1353d4e2c7706149efbc5393aa9e2cc3f.tar.gz external_llvm-1aca5bc1353d4e2c7706149efbc5393aa9e2cc3f.tar.bz2 |
Fix operand latency computation in cases where the definition operand is
implicit. e.g.
%D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def>
%Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ...
The real definition indices are 0,1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116080 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/ScheduleDAGInstrs.cpp | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index bf68c0e..c0fa9dd 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -527,6 +527,17 @@ void ScheduleDAGInstrs::ComputeOperandLatency(SUnit *Def, SUnit *Use, MachineInstr *DefMI = Def->getInstr(); int DefIdx = DefMI->findRegisterDefOperandIdx(Reg); if (DefIdx != -1) { + const MachineOperand &MO = DefMI->getOperand(DefIdx); + if (MO.isReg() && MO.isImplicit() && + DefIdx >= DefMI->getDesc().getNumOperands()) { + // This is an implicit def, getOperandLatency() won't return the correct + // latency. e.g. + // %D6<def>, %D7<def> = VLD1q16 %R2<kill>, 0, ..., %Q3<imp-def> + // %Q1<def> = VMULv8i16 %Q1<kill>, %Q3<kill>, ... + // What we want is to compute latency between def of %D6/%D7 and use of + // %Q3 instead. + DefIdx = DefMI->findRegisterDefOperandIdx(Reg, false, true, TRI); + } MachineInstr *UseMI = Use->getInstr(); // For all uses of the register, calculate the maxmimum latency int Latency = -1; |