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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-06-25 02:39:20 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-06-25 02:39:20 +0000 |
| commit | 1cb1107c660bdade8b033bae10bf223d977691e5 (patch) | |
| tree | 845973531768d7e392b4fe4708589efe9641aa30 /lib | |
| parent | 746f7cafb2d1362de62024a6e62664c3eb3999d2 (diff) | |
| download | external_llvm-1cb1107c660bdade8b033bae10bf223d977691e5.zip external_llvm-1cb1107c660bdade8b033bae10bf223d977691e5.tar.gz external_llvm-1cb1107c660bdade8b033bae10bf223d977691e5.tar.bz2 | |
R600: Fix typo in R600Schedule.td
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):
Before:
1173 Instruction Groups / 9520 dwords
After:
1167 Instruction Groups / 9510 dwords
Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184819 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/R600Schedule.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/R600/R600Schedule.td b/lib/Target/R600/R600Schedule.td index 78a460a..207233d 100644 --- a/lib/Target/R600/R600Schedule.td +++ b/lib/Target/R600/R600Schedule.td @@ -29,7 +29,7 @@ def R600_VLIW5_Itin : ProcessorItineraries < [], [ InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>, - InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>, + InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>, InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> ] @@ -40,7 +40,7 @@ def R600_VLIW4_Itin : ProcessorItineraries < [], [ InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, - InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_X, ALU_W]>]>, + InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>, InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>, InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]> ] |