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authorEvan Cheng <evan.cheng@apple.com>2007-09-27 07:35:39 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-09-27 07:35:39 +0000
commit2018681e1d5ee5b47cbfeea88bf7f41259069e39 (patch)
treee2e851b2fd4dd48b922ef40d4533fece60828017 /lib
parentdc07d96051f41a0b30c911e32ff67f8a53a5bdf8 (diff)
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Silence a compiler warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42389 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index b5c160a..509e225 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5743,7 +5743,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
case ISD::UINT_TO_FP: {
bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
- RTLIB::Libcall LC;
+ RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
if (Node->getOperand(0).getValueType() == MVT::i64) {
if (VT == MVT::f32)
LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;