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author | Chris Lattner <sabre@nondot.org> | 2010-02-12 01:15:16 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-02-12 01:15:16 +0000 |
commit | 239a1edbab18f7f42ea2e4b96efbf8474ccb3640 (patch) | |
tree | 66381a486b85a6d763f5ac8ad11ae85f26895154 /lib | |
parent | 7cdba6d1f44ac3db194a68b318f175c1f5cf5016 (diff) | |
download | external_llvm-239a1edbab18f7f42ea2e4b96efbf8474ccb3640.zip external_llvm-239a1edbab18f7f42ea2e4b96efbf8474ccb3640.tar.gz external_llvm-239a1edbab18f7f42ea2e4b96efbf8474ccb3640.tar.bz2 |
add another bit of space for new kinds of instruction prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95949 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/X86/X86.td | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 14 |
2 files changed, 10 insertions, 10 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 7919559..a8f735b 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -168,11 +168,11 @@ def X86InstrInfo : InstrInfo { 6, 7, 8, - 12, 13, - 16, - 19, + 14, + 17, 20, + 21, 24]; } diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index a6b3863..7bd3e4f 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -291,7 +291,7 @@ namespace X86II { // set, there is no prefix byte for obtaining a multibyte opcode. // Op0Shift = 8, - Op0Mask = 0xF << Op0Shift, + Op0Mask = 0x1F << Op0Shift, // TB - TwoByte - Set if this instruction has a two byte opcode, which // starts with a 0x0F byte before the real opcode. @@ -324,13 +324,13 @@ namespace X86II { // etc. We only cares about REX.W and REX.R bits and only the former is // statically determined. // - REXShift = 12, + REXShift = 13, REX_W = 1 << REXShift, //===------------------------------------------------------------------===// // This three-bit field describes the size of an immediate operand. Zero is // unused so that we can tell if we forgot to set a value. - ImmShift = 13, + ImmShift = 14, ImmMask = 7 << ImmShift, Imm8 = 1 << ImmShift, Imm16 = 2 << ImmShift, @@ -341,7 +341,7 @@ namespace X86II { // FP Instruction Classification... Zero is non-fp instruction. // FPTypeMask - Mask for all of the FP types... - FPTypeShift = 16, + FPTypeShift = 17, FPTypeMask = 7 << FPTypeShift, // NotFP - The default, set for instructions that do not use FP registers. @@ -374,17 +374,17 @@ namespace X86II { SpecialFP = 7 << FPTypeShift, // Lock prefix - LOCKShift = 19, + LOCKShift = 20, LOCK = 1 << LOCKShift, // Segment override prefixes. Currently we just need ability to address // stuff in gs and fs segments. - SegOvrShift = 20, + SegOvrShift = 21, SegOvrMask = 3 << SegOvrShift, FS = 1 << SegOvrShift, GS = 2 << SegOvrShift, - // Bits 22 -> 23 are unused + // Bit 23 is unused. OpcodeShift = 24, OpcodeMask = 0xFF << OpcodeShift }; |