diff options
author | Evan Cheng <evan.cheng@apple.com> | 2009-07-01 01:59:31 +0000 |
---|---|---|
committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-01 01:59:31 +0000 |
commit | 2578ba26e72e36dde64be0f52a2788480aad3378 (patch) | |
tree | cff0b3ae5b241d3ad9f268cdf515d8cff4f3aada /lib | |
parent | 5bcc8bd0c60cfe583ee47852950aad9e532c932e (diff) | |
download | external_llvm-2578ba26e72e36dde64be0f52a2788480aad3378.zip external_llvm-2578ba26e72e36dde64be0f52a2788480aad3378.tar.gz external_llvm-2578ba26e72e36dde64be0f52a2788480aad3378.tar.bz2 |
Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/LiveIntervalAnalysis.cpp | 93 | ||||
-rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 31 | ||||
-rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 8 | ||||
-rw-r--r-- | lib/CodeGen/VirtRegRewriter.cpp | 8 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 34 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 7 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 7 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.cpp | 14 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 36 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.cpp | 7 |
10 files changed, 183 insertions, 62 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index b017f91..9339c95 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -23,6 +23,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstr.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" @@ -33,6 +34,8 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" #include <algorithm> @@ -98,6 +101,93 @@ void LiveIntervals::releaseMemory() { } } +/// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure +/// there is one implicit_def for each use. Add isUndef marker to +/// implicit_def defs and their uses. +void LiveIntervals::processImplicitDefs() { + SmallSet<unsigned, 8> ImpDefRegs; + SmallVector<MachineInstr*, 8> ImpDefMIs; + MachineBasicBlock *Entry = mf_->begin(); + SmallPtrSet<MachineBasicBlock*,16> Visited; + for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*,16> > + DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); + DFI != E; ++DFI) { + MachineBasicBlock *MBB = *DFI; + for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); + I != E; ) { + MachineInstr *MI = &*I; + ++I; + if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) { + unsigned Reg = MI->getOperand(0).getReg(); + MI->getOperand(0).setIsUndef(); + ImpDefRegs.insert(Reg); + ImpDefMIs.push_back(MI); + continue; + } + for (unsigned i = 0; i != MI->getNumOperands(); ++i) { + MachineOperand& MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isUse()) + continue; + unsigned Reg = MO.getReg(); + if (!Reg) + continue; + if (!ImpDefRegs.count(Reg)) + continue; + MO.setIsUndef(); + if (MO.isKill() || MI->isRegTiedToDefOperand(i)) + ImpDefRegs.erase(Reg); + } + + for (unsigned i = 0; i != MI->getNumOperands(); ++i) { + MachineOperand& MO = MI->getOperand(i); + if (!MO.isReg() || !MO.isDef()) + continue; + ImpDefRegs.erase(MO.getReg()); + } + } + + // Any outstanding liveout implicit_def's? + for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) { + MachineInstr *MI = ImpDefMIs[i]; + unsigned Reg = MI->getOperand(0).getReg(); + if (TargetRegisterInfo::isPhysicalRegister(Reg)) + // Physical registers are not liveout (yet). + continue; + if (!ImpDefRegs.count(Reg)) + continue; + bool HasLocalUse = false; + for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(Reg), + RE = mri_->reg_end(); RI != RE; ) { + MachineOperand &RMO = RI.getOperand(); + MachineInstr *RMI = &*RI; + ++RI; + if (RMO.isDef()) { + // Don't expect another def of the same register. + assert(RMI == MI && + "Register with multiple defs including an implicit_def?"); + continue; + } + MachineBasicBlock *RMBB = RMI->getParent(); + if (RMBB == MBB) { + HasLocalUse = true; + continue; + } + const TargetRegisterClass* RC = mri_->getRegClass(Reg); + unsigned NewVReg = mri_->createVirtualRegister(RC); + BuildMI(*RMBB, RMI, RMI->getDebugLoc(), + tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg); + RMO.setReg(NewVReg); + RMO.setIsUndef(); + RMO.setIsKill(); + } + if (!HasLocalUse) + MI->eraseFromParent(); + } + ImpDefRegs.clear(); + ImpDefMIs.clear(); + } +} + void LiveIntervals::computeNumbering() { Index2MiMap OldI2MI = i2miMap_; std::vector<IdxMBBPair> OldI2MBB = Idx2MBBMap; @@ -299,6 +389,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { lv_ = &getAnalysis<LiveVariables>(); allocatableRegs_ = tri_->getAllocatableSet(fn); + processImplicitDefs(); computeNumbering(); computeIntervals(); @@ -1785,8 +1876,6 @@ LiveIntervals::handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm, if (MO.isReg() && MO.getReg() == li.reg) { MO.setReg(NewVReg); MO.setIsUndef(); - if (MO.isKill()) - MO.setIsKill(false); } } } diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 2caa2f9..904b4cb 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -545,26 +545,6 @@ void RALinScan::linearScan() if (!isPhys && vrm_->getPreSplitReg(cur.reg)) continue; - // A register defined by an implicit_def can be liveout the def BB and livein - // to a use BB. Add it to the livein set of the use BB's. - if (!isPhys && cur.empty()) { - if (MachineInstr *DefMI = mri_->getVRegDef(cur.reg)) { - assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF); - MachineBasicBlock *DefMBB = DefMI->getParent(); - SmallPtrSet<MachineBasicBlock*, 4> Seen; - Seen.insert(DefMBB); - for (MachineRegisterInfo::reg_iterator ri = mri_->reg_begin(cur.reg), - re = mri_->reg_end(); ri != re; ++ri) { - MachineInstr *UseMI = &*ri; - MachineBasicBlock *UseMBB = UseMI->getParent(); - if (Seen.insert(UseMBB)) { - assert(TargetRegisterInfo::isPhysicalRegister(Reg) && - "Adding a virtual register to livein set?"); - UseMBB->addLiveIn(Reg); - } - } - } - } for (LiveInterval::Ranges::const_iterator I = cur.begin(), E = cur.end(); I != E; ++I) { const LiveRange &LR = *I; @@ -905,17 +885,6 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) DOUT << tri_->getName(physReg) << '\n'; // Note the register is not really in use. vrm_->assignVirt2Phys(cur->reg, physReg); - // Since the register allocator is allowed to assign this virtual register - // physical register that overlaps other live intervals. Mark these - // operands as "Undef" which means later passes, e.g. register scavenger - // can ignore them. - for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(cur->reg), - RE = mri_->reg_end(); RI != RE; ++RI) { - MachineOperand &MO = RI.getOperand(); - MO.setIsUndef(); - if (MO.isKill()) - MO.setIsKill(false); - } return; } diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 382741e..58f4284 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -254,6 +254,8 @@ void RegScavenger::forward() { unsigned Idx = (i < NumECs) ? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second; unsigned Reg = MO.getReg(); + if (MO.isUndef()) + continue; // If it's dead upon def, then it is now free. if (MO.isDead()) { @@ -262,7 +264,9 @@ void RegScavenger::forward() { } // Skip two-address destination operand. - if (MI->isRegTiedToUseOperand(Idx)) { + unsigned UseIdx; + if (MI->isRegTiedToUseOperand(Idx, &UseIdx) && + !MI->getOperand(UseIdx).isUndef()) { assert(isUsed(Reg) && "Using an undefined register!"); continue; } @@ -316,6 +320,8 @@ void RegScavenger::backward() { ? *DefMOs[i].first : *EarlyClobberMOs[i-NumDefs].first; unsigned Idx = (i < NumECs) ? DefMOs[i].second : EarlyClobberMOs[i-NumDefs].second; + if (MO.isUndef()) + continue; // Skip two-address destination operand. if (MI->isRegTiedToUseOperand(Idx)) diff --git a/lib/CodeGen/VirtRegRewriter.cpp b/lib/CodeGen/VirtRegRewriter.cpp index bbf1e24..be0b016 100644 --- a/lib/CodeGen/VirtRegRewriter.cpp +++ b/lib/CodeGen/VirtRegRewriter.cpp @@ -2029,8 +2029,12 @@ private: if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. + // Also check if it's copying from an "undef", if so, we can't + // eliminate this or else the undef marker is lost and it will + // confuses the scavenger. This is extremely rare. unsigned Src, Dst, SrcSR, DstSR; - if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) { + if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst && + !MI.findRegisterUseOperand(Src)->isUndef()) { ++NumDCE; DOUT << "Removing now-noop copy: " << MI; SmallVector<unsigned, 2> KillRegs; @@ -2049,7 +2053,7 @@ private: Spills.disallowClobberPhysReg(VirtReg); goto ProcessNextInst; } - + // If it's not a no-op copy, it clobbers the value in the destreg. Spills.ClobberPhysReg(VirtReg); ReusedOperands.markClobbered(VirtReg); diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 35ebb7e..482867e 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -619,14 +619,19 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR)) - .addReg(SrcReg, getKillRegState(isKill)) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR)) - .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) + .addReg(DstReg, + RegState::Define | + getDeadRegState(isDead) | + getUndefRegState(isUndef)) .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg); } break; @@ -636,14 +641,22 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned PredReg = MI->getOperand(3).getReg(); if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); + bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS)) - .addReg(SrcReg).addFrameIndex(FI) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) + .addFrameIndex(FI) .addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); - NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg) - .addFrameIndex(FI) - .addImm(0).addImm(Pred).addReg(PredReg); + bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); + NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS)) + .addReg(DstReg, + RegState::Define | + getDeadRegState(isDead) | + getUndefRegState(isUndef)) + .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; } @@ -653,14 +666,19 @@ foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, if (OpNum == 0) { // move -> store unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD)) - .addReg(SrcReg, getKillRegState(isKill)) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } else { // move -> load unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD)) - .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) + .addReg(DstReg, + RegState::Define | + getDeadRegState(isDead) | + getUndefRegState(isUndef)) .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg); } break; diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 229f9d4..203c7b1 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -289,19 +289,22 @@ MachineInstr *AlphaInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (Ops[0] == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(InReg, getKillRegState(isKill)) + .addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) - .addReg(OutReg, RegState::Define | getDeadRegState(isDead)) + .addReg(OutReg, RegState::Define | getDeadRegState(isDead) | + getUndefRegState(isUndef)) .addFrameIndex(FrameIndex) .addReg(Alpha::F31); } diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 4af995a..e629c8d 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -491,19 +491,22 @@ SPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); if (FrameIndex < SPUFrameInfo::maxFrameOffset()) { MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(SPU::STQDr32)); - MIB.addReg(InReg, getKillRegState(isKill)); + MIB.addReg(InReg, getKillRegState(isKill) | getUndefRegState(isUndef)); NewMI = addFrameReference(MIB, FrameIndex); } } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc)); - MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead)); + MIB.addReg(OutReg, RegState::Define | getDeadRegState(isDead) | + getUndefRegState(isUndef)); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32; NewMI = addFrameReference(MIB, FrameIndex); diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 92af973..c2b8764 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -291,14 +291,17 @@ foldMemoryOperandImpl(MachineFunction &MF, if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(2).getReg(); bool isKill = MI->getOperand(2).isKill(); + bool isUndef = MI->getOperand(2).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW)) - .addReg(SrcReg, getKillRegState(isKill)) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addImm(0).addFrameIndex(FI); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW)) - .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | + getUndefRegState(isUndef)) .addImm(0).addFrameIndex(FI); } } @@ -321,14 +324,17 @@ foldMemoryOperandImpl(MachineFunction &MF, if (Ops[0] == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(2).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc)) - .addReg(SrcReg, getKillRegState(isKill)) + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)) .addImm(0).addFrameIndex(FI) ; } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc)) - .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) + .addReg(DstReg, RegState::Define | getDeadRegState(isDead) | + getUndefRegState(isUndef)) .addImm(0).addFrameIndex(FI); } } diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 778f034..0aafe22 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -691,16 +691,21 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW)) - .addReg(InReg, getKillRegState(isKill)), + .addReg(InReg, + getKillRegState(isKill) | + getUndefRegState(isUndef)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ)) .addReg(OutReg, RegState::Define | - getDeadRegState(isDead)), + getDeadRegState(isDead) | + getUndefRegState(isUndef)), FrameIndex); } } else if ((Opc == PPC::OR8 && @@ -708,48 +713,63 @@ MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD)) - .addReg(InReg, getKillRegState(isKill)), + .addReg(InReg, + getKillRegState(isKill) | + getUndefRegState(isUndef)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD)) .addReg(OutReg, RegState::Define | - getDeadRegState(isDead)), + getDeadRegState(isDead) | + getUndefRegState(isUndef)), FrameIndex); } } else if (Opc == PPC::FMRD) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFD)) - .addReg(InReg, getKillRegState(isKill)), + .addReg(InReg, + getKillRegState(isKill) | + getUndefRegState(isUndef)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFD)) .addReg(OutReg, RegState::Define | - getDeadRegState(isDead)), + getDeadRegState(isDead) | + getUndefRegState(isUndef)), FrameIndex); } } else if (Opc == PPC::FMRS) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STFS)) - .addReg(InReg, getKillRegState(isKill)), + .addReg(InReg, + getKillRegState(isKill) | + getUndefRegState(isUndef)), FrameIndex); } else { // move -> load unsigned OutReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LFS)) .addReg(OutReg, RegState::Define | - getDeadRegState(isDead)), + getDeadRegState(isDead) | + getUndefRegState(isUndef)), FrameIndex); } } diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index d2f6b9b..12c286a 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -256,17 +256,20 @@ MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (OpNum == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); + bool isUndef = MI->getOperand(1).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(isFloat ? SP::STFri : SP::STDFri)) .addFrameIndex(FI) .addImm(0) - .addReg(SrcReg, getKillRegState(isKill)); + .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); + bool isUndef = MI->getOperand(0).isUndef(); NewMI = BuildMI(MF, MI->getDebugLoc(), get(isFloat ? SP::LDFri : SP::LDDFri)) - .addReg(DstReg, RegState::Define | getDeadRegState(isDead)) + .addReg(DstReg, RegState::Define | + getDeadRegState(isDead) | getUndefRegState(isUndef)) .addFrameIndex(FI) .addImm(0); } |