Add support for TargetConstantPool nodes to the dag isel emitter, and use

them in the PPC backend, to simplify some logic out of Select and
SelectAddr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 45 insertions, 30 deletions

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index c667487..620b643 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -532,6 +532,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
   case ISD::TargetFrameIndex:
   case ISD::Register:
   case ISD::TargetConstant:
+  case ISD::TargetConstantPool:
   case ISD::GlobalAddress:
   case ISD::TargetGlobalAddress:
   case ISD::ExternalSymbol:
@@ -679,7 +680,8 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
         Extend = true;
       }
 
-      SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
+      SDOperand CPIdx = 
+        LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
       if (Extend) {
         Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
                                 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 8517bf7..01d089d 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -423,7 +423,8 @@ bool PPCDAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
       assert(!cast<ConstantSDNode>(Addr.getOperand(1).getOperand(1))->getValue()
              && "Cannot handle constant offsets yet!");
       Op1 = Addr.getOperand(1).getOperand(0);  // The global address.
-      assert(Op1.getOpcode() == ISD::TargetGlobalAddress);
+      assert(Op1.getOpcode() == ISD::TargetGlobalAddress ||
+             Op1.getOpcode() == ISD::TargetConstantPool);
       Op2 = Select(Addr.getOperand(0));
       return false;   // [&g+r]
     } else {
@@ -433,20 +434,11 @@ bool PPCDAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1,
     }
   }
 
-  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) {
-    Op1 = getI32Imm(0);
+  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
     Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
-    return false;
-  } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) {
-    Op1 = Addr;
-    if (PICEnabled)
-      Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1);
-    else
-      Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1);
-    return false;
-  }
+  else
+    Op2 = Select(Addr);
   Op1 = getI32Imm(0);
-  Op2 = Select(Addr);
   return false;
 }
 
@@ -893,17 +885,6 @@ SDOperand PPCDAGToDAGISel::Select(SDOperand Op) {
                             CurDAG->getTargetFrameIndex(FI, MVT::i32),
                             getI32Imm(0));
   }
-  case ISD::ConstantPool: {
-    Constant *C = cast<ConstantPoolSDNode>(N)->get();
-    SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
-    if (PICEnabled)
-      Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
-    else
-      Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
-    if (N->hasOneUse())
-      return CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
-    return CodeGenMap[Op] = CurDAG->getTargetNode(PPC::LA, MVT::i32, Tmp, CPI);
-  }
   case ISD::FADD: {
     MVT::ValueType Ty = N->getValueType(0);
     if (!NoExcessFPPrecision) {  // Match FMA ops
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 76a8f01..27df47c 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -94,9 +94,10 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
   // PowerPC doesn't have line number support yet.
   setOperationAction(ISD::LOCATION, MVT::Other, Expand);
   
-  // We want to legalize GlobalAddress into the appropriate instructions to
-  // materialize the address.
+  // We want to legalize GlobalAddress and ConstantPool nodes into the 
+  // appropriate instructions to materialize the address.
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+  setOperationAction(ISD::ConstantPool,  MVT::i32, Custom);
   
   if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
     // They also have instructions for converting between i64 and fp.
@@ -341,14 +342,40 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
                                       Tmp4, Tmp6, ISD::SETLE);
     return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
   }
+  case ISD::ConstantPool: {
+    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
+    SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32);
+    SDOperand Zero = DAG.getConstant(0, MVT::i32);
+    
+    if (PPCGenerateStaticCode) {
+      // Generate non-pic code that has direct accesses to the constant pool.
+      // The address of the global is just (hi(&g)+lo(&g)).
+      SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+      SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+      return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+    }
+    
+    // Only lower ConstantPool on Darwin.
+    if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
+    SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
+    if (PICEnabled) {
+      // With PIC, the first instruction is actually "GR+hi(&G)".
+      Hi = DAG.getNode(ISD::ADD, MVT::i32,
+                       DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
+    }
+
+    SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
+    Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
+    return Lo;
+  }
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
     SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
     SDOperand Zero = DAG.getConstant(0, MVT::i32);
 
     if (PPCGenerateStaticCode) {
-      // Generate non-pic code that has direct accesses to globals.  To do this
-      // the address of the global is just (hi(&g)+lo(&g)).
+      // Generate non-pic code that has direct accesses to globals.
+      // The address of the global is just (hi(&g)+lo(&g)).
       SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
       SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
       return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 03f0c6e..51f0525 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -165,7 +165,6 @@ def crbitm: Operand<i8> {
 }
 
 
-
 //===----------------------------------------------------------------------===//
 // PowerPC Instruction Definitions.
 
@@ -943,8 +942,12 @@ def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
 // Hi and Lo for Darwin Global Addresses.
 def : Pat<(PPChi tglobaladdr:$in, (i32 0)), (LIS tglobaladdr:$in)>;
 def : Pat<(PPClo tglobaladdr:$in, (i32 0)), (LI tglobaladdr:$in)>;
+def : Pat<(PPChi tconstpool:$in, (i32 0)), (LIS tconstpool:$in)>;
+def : Pat<(PPClo tconstpool:$in, (i32 0)), (LI tconstpool:$in)>;
 def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
           (ADDIS GPRC:$in, tglobaladdr:$g)>;
+def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
+          (ADDIS GPRC:$in, tconstpool:$g)>;
 
 // Standard shifts.  These are represented separately from the real shifts above
 // so that we can distinguish between shifts that allow 5-bit and 6-bit shift
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index ef62013..95ec835 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -174,6 +174,8 @@ def globaladdr : SDNode<"ISD::GlobalAddress", SDTImm, [],
                         "GlobalAddressSDNode">;
 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTImm, [],
                         "GlobalAddressSDNode">;
+def tconstpool  : SDNode<"ISD::TargetConstantPool", SDTImm, [],
+                        "ConstantPoolSDNode">;
 def add        : SDNode<"ISD::ADD"       , SDTIntBinOp   ,
                         [SDNPCommutative, SDNPAssociative]>;
 def sub        : SDNode<"ISD::SUB"       , SDTIntBinOp>;