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author | Chris Lattner <sabre@nondot.org> | 2010-11-15 05:19:05 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-11-15 05:19:05 +0000 |
commit | 2ac190238e88b21e716e2853900b5076c9013410 (patch) | |
tree | 96d31431369e0b53130604939ace6898f13b505d /lib | |
parent | 513dbf1af06d0bc530dd6f17da320d2fb40b3a28 (diff) | |
download | external_llvm-2ac190238e88b21e716e2853900b5076c9013410.zip external_llvm-2ac190238e88b21e716e2853900b5076c9013410.tar.gz external_llvm-2ac190238e88b21e716e2853900b5076c9013410.tar.bz2 |
add fields to the .td files unconditionally, simplifying tblgen a bit.
Switch the ARM backend to use 'let' instead of 'set' with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMAsmPrinter.cpp | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 10 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 40 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 4 | ||||
-rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 2 | ||||
-rw-r--r-- | lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp | 2 | ||||
-rw-r--r-- | lib/Target/X86/X86MCCodeEmitter.cpp | 2 |
7 files changed, 31 insertions, 31 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 3a97a69..e7ac48c 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -200,7 +200,7 @@ namespace { MachineLocation getDebugValueLocation(const MachineInstr *MI) const { MachineLocation Location; - assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); + assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!"); // Frame address. Currently handles register +- offset only. if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm()); diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index aeb2f1d..774c441 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -154,13 +154,13 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR), // Conditional code result for instructions whose 's' bit is set, e.g. subs. def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> { - string EncoderMethod = "getCCOutOpValue"; + let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; } // Same as cc_out except it defaults to setting CPSR. def s_cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 CPSR))> { - string EncoderMethod = "getCCOutOpValue"; + let EncoderMethod = "getCCOutOpValue"; let PrintMethod = "printSBitModifierOperand"; } @@ -1675,7 +1675,7 @@ class NLdSt<bit op23, bits<2> op21_20, bits<4> op11_8, bits<4> op7_4, let Inst{11-8} = op11_8; let Inst{7-4} = op7_4; - string PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; + let PostEncoderMethod = "NEONThumb2LoadStorePostEncoder"; bits<5> Vd; bits<6> Rn; @@ -1718,7 +1718,7 @@ class NDataI<dag oops, dag iops, Format f, InstrItinClass itin, : NeonI<oops, iops, AddrModeNone, IndexModeNone, f, itin, opc, dt, asm, cstr, pattern> { let Inst{31-25} = 0b1111001; - string PostEncoderMethod = "NEONThumb2DataIPostEncoder"; + let PostEncoderMethod = "NEONThumb2DataIPostEncoder"; } class NDataXI<dag oops, dag iops, Format f, InstrItinClass itin, @@ -1894,7 +1894,7 @@ class NVLaneOp<bits<8> opcod1, bits<4> opcod2, bits<2> opcod3, let Pattern = pattern; list<Predicate> Predicates = [HasNEON]; - string PostEncoderMethod = "NEONThumb2DupPostEncoder"; + let PostEncoderMethod = "NEONThumb2DupPostEncoder"; bits<5> V; bits<4> R; diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index f163c1b..3ba0ceb 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -231,7 +231,7 @@ def bf_inv_mask_imm : Operand<i32>, PatLeaf<(imm), [{ return ARM::isBitFieldInvertedMask(N->getZExtValue()); }] > { - string EncoderMethod = "getBitfieldInvertedMaskOpValue"; + let EncoderMethod = "getBitfieldInvertedMaskOpValue"; let PrintMethod = "printBitfieldInvMaskImmOperand"; } @@ -275,13 +275,13 @@ def sube_live_carry : // Branch target. def brtarget : Operand<OtherVT> { - string EncoderMethod = "getBranchTargetOpValue"; + let EncoderMethod = "getBranchTargetOpValue"; } // Call target. def bltarget : Operand<i32> { // Encoded the same as branch targets. - string EncoderMethod = "getBranchTargetOpValue"; + let EncoderMethod = "getBranchTargetOpValue"; } // A list of registers separated by comma. Used by load/store multiple. @@ -291,7 +291,7 @@ def RegListAsmOperand : AsmOperandClass { } def reglist : Operand<i32> { - string EncoderMethod = "getRegisterListOpValue"; + let EncoderMethod = "getRegisterListOpValue"; let ParserMatchClass = RegListAsmOperand; let PrintMethod = "printRegisterList"; } @@ -314,14 +314,14 @@ def pclabel : Operand<i32> { } def neon_vcvt_imm32 : Operand<i32> { - string EncoderMethod = "getNEONVcvtImm32OpValue"; + let EncoderMethod = "getNEONVcvtImm32OpValue"; } // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24. def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{ - int32_t v = (int32_t)N->getZExtValue(); - return v == 8 || v == 16 || v == 24; }]> { - string EncoderMethod = "getRotImmOpValue"; + int32_t v = (int32_t)N->getZExtValue(); + return v == 8 || v == 16 || v == 24; }]> { + let EncoderMethod = "getRotImmOpValue"; } // shift_imm: An integer that encodes a shift amount and the type of shift @@ -335,14 +335,14 @@ def shift_imm : Operand<i32> { def so_reg : Operand<i32>, // reg reg imm ComplexPattern<i32, 3, "SelectShifterOperandReg", [shl,srl,sra,rotr]> { - string EncoderMethod = "getSORegOpValue"; + let EncoderMethod = "getSORegOpValue"; let PrintMethod = "printSORegOperand"; let MIOperandInfo = (ops GPR, GPR, i32imm); } def shift_so_reg : Operand<i32>, // reg reg imm ComplexPattern<i32, 3, "SelectShiftShifterOperandReg", [shl,srl,sra,rotr]> { - string EncoderMethod = "getSORegOpValue"; + let EncoderMethod = "getSORegOpValue"; let PrintMethod = "printSORegOperand"; let MIOperandInfo = (ops GPR, GPR, i32imm); } @@ -353,7 +353,7 @@ def shift_so_reg : Operand<i32>, // reg reg imm // into so_imm instructions: the 8-bit immediate is the least significant bits // [bits 0-7], the 4-bit shift amount is the next 4 bits [bits 8-11]. def so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_so_imm(N); }]> { - string EncoderMethod = "getSOImmOpValue"; + let EncoderMethod = "getSOImmOpValue"; let PrintMethod = "printSOImmOperand"; } @@ -407,7 +407,7 @@ def imm0_31 : Operand<i32>, PatLeaf<(imm), [{ def imm0_31_m1 : Operand<i32>, PatLeaf<(imm), [{ return (int32_t)N->getZExtValue() < 32; }]> { - string EncoderMethod = "getImmMinusOneOpValue"; + let EncoderMethod = "getImmMinusOneOpValue"; } // Define ARM specific addressing modes. @@ -421,7 +421,7 @@ def addrmode_imm12 : Operand<i32>, // #0 and #-0 differently. We flag #-0 as the magic value INT32_MIN. All other // immediate values are as normal. - string EncoderMethod = "getAddrModeImm12OpValue"; + let EncoderMethod = "getAddrModeImm12OpValue"; let PrintMethod = "printAddrModeImm12Operand"; let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); } @@ -429,7 +429,7 @@ def addrmode_imm12 : Operand<i32>, // def ldst_so_reg : Operand<i32>, ComplexPattern<i32, 3, "SelectLdStSOReg", []> { - string EncoderMethod = "getLdStSORegOpValue"; + let EncoderMethod = "getLdStSORegOpValue"; // FIXME: Simplify the printer let PrintMethod = "printAddrMode2Operand"; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); @@ -456,7 +456,7 @@ def am2offset : Operand<i32>, // def addrmode3 : Operand<i32>, ComplexPattern<i32, 3, "SelectAddrMode3", []> { - string EncoderMethod = "getAddrMode3OpValue"; + let EncoderMethod = "getAddrMode3OpValue"; let PrintMethod = "printAddrMode3Operand"; let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm); } @@ -464,7 +464,7 @@ def addrmode3 : Operand<i32>, def am3offset : Operand<i32>, ComplexPattern<i32, 2, "SelectAddrMode3Offset", [], [SDNPWantRoot]> { - string EncoderMethod = "getAddrMode3OffsetOpValue"; + let EncoderMethod = "getAddrMode3OffsetOpValue"; let PrintMethod = "printAddrMode3OffsetOperand"; let MIOperandInfo = (ops GPR, i32imm); } @@ -472,7 +472,7 @@ def am3offset : Operand<i32>, // ldstm_mode := {ia, ib, da, db} // def ldstm_mode : OptionalDefOperand<OtherVT, (ops i32), (ops (i32 1))> { - string EncoderMethod = "getLdStmModeOpValue"; + let EncoderMethod = "getLdStmModeOpValue"; let PrintMethod = "printLdStmModeOperand"; } @@ -488,7 +488,7 @@ def addrmode5 : Operand<i32>, let PrintMethod = "printAddrMode5Operand"; let MIOperandInfo = (ops GPR:$base, i32imm); let ParserMatchClass = MemMode5AsmOperand; - string EncoderMethod = "getAddrMode5OpValue"; + let EncoderMethod = "getAddrMode5OpValue"; } // addrmode6 := reg with optional writeback @@ -497,13 +497,13 @@ def addrmode6 : Operand<i32>, ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{ let PrintMethod = "printAddrMode6Operand"; let MIOperandInfo = (ops GPR:$addr, i32imm); - string EncoderMethod = "getAddrMode6AddressOpValue"; + let EncoderMethod = "getAddrMode6AddressOpValue"; } def am6offset : Operand<i32> { let PrintMethod = "printAddrMode6OffsetOperand"; let MIOperandInfo = (ops GPR); - string EncoderMethod = "getAddrMode6OffsetOpValue"; + let EncoderMethod = "getAddrMode6OffsetOpValue"; } // addrmodepc := pc + reg diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index ad017a7..a8de8ab 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -31,7 +31,7 @@ def tb_addrmode : Operand<i32> { def t2_so_reg : Operand<i32>, // reg imm ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", [shl,srl,sra,rotr]> { - string EncoderMethod = "getT2SORegOpValue"; + let EncoderMethod = "getT2SORegOpValue"; let PrintMethod = "printT2SOOperand"; let MIOperandInfo = (ops rGPR, i32imm); } @@ -53,7 +53,7 @@ def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ // into t2_so_imm instructions: the 8-bit immediate is the least significant // bits [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11]. def t2_so_imm : Operand<i32>, PatLeaf<(imm), [{ return Pred_t2_so_imm(N); }]> { - string EncoderMethod = "getT2SOImmOpValue"; + let EncoderMethod = "getT2SOImmOpValue"; } // t2_so_imm_not - Match an immediate that is a complement diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 0b896ed..b156755 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "arm-emitter" +#define DEBUG_TYPE "mccodeemitter" #include "ARM.h" #include "ARMAddressingModes.h" #include "ARMFixupKinds.h" diff --git a/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp b/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp index adbec06..19dc89b 100644 --- a/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp +++ b/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "mblaze-emitter" +#define DEBUG_TYPE "mccodeemitter" #include "MBlaze.h" #include "MBlazeInstrInfo.h" #include "MBlazeFixupKinds.h" diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp index 950fdf1..fea37f8 100644 --- a/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/X86MCCodeEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "x86-emitter" +#define DEBUG_TYPE "mccodeemitter" #include "X86.h" #include "X86InstrInfo.h" #include "X86FixupKinds.h" |