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| author | Evan Cheng <evan.cheng@apple.com> | 2009-01-03 04:24:44 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-01-03 04:24:44 +0000 |
| commit | 2b5a621e99b3e8e61f9543b3c8b767b374f1315c (patch) | |
| tree | ff5d168a5eebc6dbb83ddca68968831eb0c59eb3 /lib | |
| parent | 5211b42949b3302635f8b8c869aa84430708b357 (diff) | |
| download | external_llvm-2b5a621e99b3e8e61f9543b3c8b767b374f1315c.zip external_llvm-2b5a621e99b3e8e61f9543b3c8b767b374f1315c.tar.gz external_llvm-2b5a621e99b3e8e61f9543b3c8b767b374f1315c.tar.bz2 | |
Add Intel processors core i7 and atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61603 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 3 |
2 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td index 8867298..7a2f257 100644 --- a/lib/Target/X86/X86.td +++ b/lib/Target/X86/X86.td @@ -76,6 +76,8 @@ def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>; def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>; def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>; +def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>; +def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>; def : Proc<"k6", [FeatureMMX]>; def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>; diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index a7df68b..c6cda56 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -204,6 +204,7 @@ static const char *GetCurrentX86CPU() { unsigned Family = 0; unsigned Model = 0; DetectFamilyModel(EAX, Family, Model); + bool HasSSE42 = (ECX >> 19) & 0x1; X86::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); bool Em64T = (EDX >> 29) & 0x1; @@ -254,7 +255,7 @@ static const char *GetCurrentX86CPU() { case 28: // Intel Atom, and Core i7 both have this model. // Atom has SSSE3, Core i7 has SSE4.2 - return "core2"; + return (HasSSE42) ? "corei7" : "atom"; default: return (Em64T) ? "x86-64" : "pentium4"; } |