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| author | Bob Wilson <bob.wilson@apple.com> | 2010-11-03 16:24:50 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-11-03 16:24:50 +0000 |
| commit | 3468c2ee20e26ded1a5182edcc72e36fb09c909b (patch) | |
| tree | e4274850a1362ebe62915a022704ed44b2256786 /lib | |
| parent | d66f2b74f2f01bb1f6c7d0f1b8408bd24ffa654c (diff) | |
| download | external_llvm-3468c2ee20e26ded1a5182edcc72e36fb09c909b.zip external_llvm-3468c2ee20e26ded1a5182edcc72e36fb09c909b.tar.gz external_llvm-3468c2ee20e26ded1a5182edcc72e36fb09c909b.tar.bz2 | |
Check for extractelement with a variable operand for the element number.
For NEON we had been assuming this was always an immediate constant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 25 |
1 files changed, 15 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index a9a8c88..2e4fa32 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -84,8 +84,7 @@ void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT ElemTy = VT.getVectorElementType(); if (ElemTy != MVT::i64 && ElemTy != MVT::f64) setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); - if (ElemTy == MVT::i8 || ElemTy == MVT::i16) - setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); if (ElemTy != MVT::i32) { setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); @@ -3777,14 +3776,19 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { } static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { - EVT VT = Op.getValueType(); - DebugLoc dl = Op.getDebugLoc(); - SDValue Vec = Op.getOperand(0); + // EXTRACT_VECTOR_ELT is legal only for immediate indexes. SDValue Lane = Op.getOperand(1); - assert(VT == MVT::i32 && - Vec.getValueType().getVectorElementType().getSizeInBits() < 32 && - "unexpected type for custom-lowering vector extract"); - return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); + if (!isa<ConstantSDNode>(Lane)) + return SDValue(); + + SDValue Vec = Op.getOperand(0); + if (Op.getValueType() == MVT::i32 && + Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { + DebugLoc dl = Op.getDebugLoc(); + return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); + } + + return Op; } static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { @@ -4923,7 +4927,8 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, if (VT == MVT::i32 && (EltVT == MVT::i8 || EltVT == MVT::i16) && - TLI.isTypeLegal(Vec.getValueType())) { + TLI.isTypeLegal(Vec.getValueType()) && + isa<ConstantSDNode>(Lane)) { unsigned Opc = 0; switch (N->getOpcode()) { |