Fixed spelling and grammar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8489 91177308-0d34-0410-b5e6-96231b3b80d8

14 files changed, 57 insertions, 57 deletions

diff --git a/lib/Archive/ArchiveReader.cpp b/lib/Archive/ArchiveReader.cpp
index f631f2d..6a3f7ab 100644
--- a/lib/Archive/ArchiveReader.cpp
+++ b/lib/Archive/ArchiveReader.cpp
@@ -130,7 +130,7 @@ static bool ReadArchiveBuffer(const std::string &Filename,
 }
 
 
-// ReadArchiveFile - Read bytecode files from the specfied .a file, returning
+// ReadArchiveFile - Read bytecode files from the specified .a file, returning
 // true on error, or false on success.  This does not support reading files from
 // standard input.
 //
diff --git a/lib/Bytecode/Archive/ArchiveReader.cpp b/lib/Bytecode/Archive/ArchiveReader.cpp
index f631f2d..6a3f7ab 100644
--- a/lib/Bytecode/Archive/ArchiveReader.cpp
+++ b/lib/Bytecode/Archive/ArchiveReader.cpp
@@ -130,7 +130,7 @@ static bool ReadArchiveBuffer(const std::string &Filename,
 }
 
 
-// ReadArchiveFile - Read bytecode files from the specfied .a file, returning
+// ReadArchiveFile - Read bytecode files from the specified .a file, returning
 // true on error, or false on success.  This does not support reading files from
 // standard input.
 //
diff --git a/lib/Bytecode/Reader/ArchiveReader.cpp b/lib/Bytecode/Reader/ArchiveReader.cpp
index f631f2d..6a3f7ab 100644
--- a/lib/Bytecode/Reader/ArchiveReader.cpp
+++ b/lib/Bytecode/Reader/ArchiveReader.cpp
@@ -130,7 +130,7 @@ static bool ReadArchiveBuffer(const std::string &Filename,
 }
 
 
-// ReadArchiveFile - Read bytecode files from the specfied .a file, returning
+// ReadArchiveFile - Read bytecode files from the specified .a file, returning
 // true on error, or false on success.  This does not support reading files from
 // standard input.
 //
diff --git a/lib/Bytecode/Reader/ConstantReader.cpp b/lib/Bytecode/Reader/ConstantReader.cpp
index 13cdc85..25abb79 100644
--- a/lib/Bytecode/Reader/ConstantReader.cpp
+++ b/lib/Bytecode/Reader/ConstantReader.cpp
@@ -4,7 +4,7 @@
 // constant pools.
 // 
 // Note that this library should be as fast as possible, reentrant, and 
-// threadsafe!!
+// thread-safe!!
 //
 //===----------------------------------------------------------------------===//
 
@@ -113,12 +113,12 @@ void BytecodeParser::refineAbstractType(const DerivedType *OldType,
 
 
 
-// parseTypeConstants - We have to use this wierd code to handle recursive
+// parseTypeConstants - We have to use this weird code to handle recursive
 // types.  We know that recursive types will only reference the current slab of
 // values in the type plane, but they can forward reference types before they
 // have been read.  For example, Type #0 might be '{ Ty#1 }' and Type #1 might
 // be 'Ty#0*'.  When reading Type #0, type number one doesn't exist.  To fix
-// this ugly problem, we pesimistically insert an opaque type for each type we
+// this ugly problem, we pessimistically insert an opaque type for each type we
 // are about to read.  This means that forward references will resolve to
 // something and when we reread the type later, we can replace the opaque type
 // with a new resolved concrete type.
@@ -327,7 +327,7 @@ bool BytecodeParser::parseConstantValue(const unsigned char *&Buf,
         if (!(GV = dyn_cast<GlobalValue>(Val))) return true;
         BCR_TRACE(5, "Value Found in ValueTable!\n");
       } else if (RevisionNum > 0) {
-        // Revision #0 could have forward references to globals that were wierd.
+        // Revision #0 could have forward references to globals that were weird.
         // We got rid of this in subsequent revs.
         return true;
       } else {         // Nope... find or create a forward ref. for it
diff --git a/lib/Bytecode/Reader/InstructionReader.cpp b/lib/Bytecode/Reader/InstructionReader.cpp
index 407777c..0ab2655 100644
--- a/lib/Bytecode/Reader/InstructionReader.cpp
+++ b/lib/Bytecode/Reader/InstructionReader.cpp
@@ -204,7 +204,7 @@ bool BytecodeParser::ParseInstruction(const unsigned char *&Buf,
       new SwitchInst(getValue(Raw.Ty, Raw.Arg1), 
                      cast<BasicBlock>(getValue(Type::LabelTy, Raw.Arg2)));
     Res = I;
-    if (Raw.NumOperands < 3) return false;  // No destinations?  Wierd.
+    if (Raw.NumOperands < 3) return false;  // No destinations?  Weird.
 
     if (Raw.NumOperands == 3 || Raw.VarArgs->size() & 1) {
       std::cerr << "Switch statement with odd number of arguments!\n";
diff --git a/lib/Bytecode/Reader/Reader.cpp b/lib/Bytecode/Reader/Reader.cpp
index 8a56f22..5277806 100644
--- a/lib/Bytecode/Reader/Reader.cpp
+++ b/lib/Bytecode/Reader/Reader.cpp
@@ -436,7 +436,7 @@ bool BytecodeParser::ParseModuleGlobalInfo(const unsigned char *&Buf,
     BCR_TRACE(2, "Global Variable of type: " << *Ty << "\n");
     ResolveReferencesToValue(GV, (unsigned)DestSlot);
 
-    if (VarType & 2) { // Does it have an initalizer?
+    if (VarType & 2) { // Does it have an initializer?
       unsigned InitSlot;
       if (read_vbr(Buf, End, InitSlot)) return true;
       GlobalInits.push_back(std::make_pair(GV, InitSlot));
diff --git a/lib/Bytecode/Writer/InstructionWriter.cpp b/lib/Bytecode/Writer/InstructionWriter.cpp
index 64dc65e..da32c03 100644
--- a/lib/Bytecode/Writer/InstructionWriter.cpp
+++ b/lib/Bytecode/Writer/InstructionWriter.cpp
@@ -52,7 +52,7 @@ static void outputInstructionFormat0(const Instruction *I, unsigned Opcode,
 }
 
 
-// outputInstrVarArgsCall - Output the obsurdly annoying varargs function calls.
+// outputInstrVarArgsCall - Output the absurdly annoying varargs function calls.
 // This are more annoying than most because the signature of the call does not
 // tell us anything about the types of the arguments in the varargs portion.
 // Because of this, we encode (as type 0) all of the argument types explicitly
@@ -271,6 +271,6 @@ void BytecodeWriter::processInstruction(const Instruction &I) {
   }
 
   // If we weren't handled before here, we either have a large number of
-  // operands or a large operand index that we are refering to.
+  // operands or a large operand index that we are referring to.
   outputInstructionFormat0(&I, Opcode, Table, Type, Out);
 }
diff --git a/lib/Bytecode/Writer/Writer.cpp b/lib/Bytecode/Writer/Writer.cpp
index 096dc69..b119c3d 100644
--- a/lib/Bytecode/Writer/Writer.cpp
+++ b/lib/Bytecode/Writer/Writer.cpp
@@ -3,7 +3,7 @@
 // This library implements the functionality defined in llvm/Bytecode/Writer.h
 //
 // Note that this file uses an unusual technique of outputting all the bytecode
-// to a deque of unsigned char's, then copies the deque to an ostream.  The
+// to a deque of unsigned chare, then copies the deque to an ostream.  The
 // reason for this is that we must do "seeking" in the stream to do back-
 // patching, and some very important ostreams that we want to support (like
 // pipes) do not support seeking.  :( :( :(
@@ -143,7 +143,7 @@ void BytecodeWriter::outputConstants(bool isFunction) {
       const std::vector<const Value*> &Plane = Table.getPlane(pno);
       if (!Plane.empty()) {              // Skip empty type planes...
         unsigned ValNo = 0;
-        if (isFunction)                  // Don't reemit module constants
+        if (isFunction)                  // Don't re-emit module constants
           ValNo += Table.getModuleLevel(pno);
         
         if (pno >= Type::FirstDerivedTyID) {
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 1e44e17..a04d4b8 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -104,7 +104,7 @@ PhyRegAlloc::~PhyRegAlloc() {
 } 
 
 //----------------------------------------------------------------------------
-// This method initally creates interference graphs (one in each reg class)
+// This method initially creates interference graphs (one in each reg class)
 // and IGNodeList (one in each IG). The actual nodes will be pushed later. 
 //----------------------------------------------------------------------------
 void PhyRegAlloc::createIGNodeListsAndIGs() {
@@ -145,7 +145,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
 
 //----------------------------------------------------------------------------
 // This method will add all interferences at for a given instruction.
-// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg 
+// Interference occurs only if the LR of Def (Inst or Arg) is of the same reg 
 // class as that of live var. The live var passed to this function is the 
 // LVset AFTER the instruction
 //----------------------------------------------------------------------------
@@ -290,9 +290,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
       bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
 
       if (isCallInst ) {
-	// set the isCallInterference flag of each live range wich extends
-	// accross this call instruction. This information is used by graph
-	// coloring algo to avoid allocating volatile colors to live ranges
+	// set the isCallInterference flag of each live range which extends
+	// across this call instruction. This information is used by graph
+	// coloring algorithm to avoid allocating volatile colors to live ranges
 	// that span across calls (since they have to be saved/restored)
 	//
 	setCallInterferences(MInst, &LVSetAI);
@@ -331,7 +331,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
   } // for all BBs in function
 
 
-  // add interferences for function arguments. Since there are no explict 
+  // add interferences for function arguments. Since there are no explicit 
   // defs in the function for args, we have to add them manually
   //  
   addInterferencesForArgs();          
@@ -343,7 +343,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
 
 
 //--------------------------------------------------------------------------
-// Pseudo instructions will be exapnded to multiple instructions by the
+// Pseudo-instructions will be expanded to multiple instructions by the
 // assembler. Consequently, all the opernds must get distinct registers.
 // Therefore, we mark all operands of a pseudo instruction as they interfere
 // with one another.
@@ -404,7 +404,7 @@ void PhyRegAlloc::addInterferencesForArgs() {
 
 //----------------------------------------------------------------------------
 // This method is called after register allocation is complete to set the
-// allocated reisters in the machine code. This code will add register numbers
+// allocated registers in the machine code. This code will add register numbers
 // to MachineOperands that contain a Value. Also it calls target specific
 // methods to produce caller saving instructions. At the end, it adds all
 // additional instructions produced by the register allocator to the 
@@ -722,7 +722,7 @@ void PhyRegAlloc::updateMachineCode()
 // if it contains many spilled operands. Each time it is called, it finds
 // a register which is not live at that instruction and also which is not
 // used by other spilled operands of the same instruction. Then it uses
-// this register temporarily to accomodate the spilled value.
+// this register temporarily to accommodate the spilled value.
 //----------------------------------------------------------------------------
 
 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, 
@@ -835,7 +835,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
 
 
 //----------------------------------------------------------------------------
-// This method inserts caller saving/restoring instructons before/after
+// This method inserts caller saving/restoring instructions before/after
 // a call machine instruction. The caller saving/restoring instructions are
 // inserted like:
 //    ** caller saving instructions
@@ -1077,7 +1077,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
 
 //----------------------------------------------------------------------------
 // This method is called to get a new unused register that can be used
-// to accomodate a temporary value.  This method may be called several times
+// to accommodate a temporary value.  This method may be called several times
 // for a single machine instruction.  Each time it is called, it finds a
 // register which is not live at that instruction and also which is not used
 // by other spilled operands of the same instruction.  Return register number
@@ -1370,7 +1370,7 @@ void PhyRegAlloc::markUnusableSugColors()
 
 //----------------------------------------------------------------------------
 // The following method will set the stack offsets of the live ranges that
-// are decided to be spillled. This must be called just after coloring the
+// are decided to be spilled. This must be called just after coloring the
 // LRs using the graph coloring algo. For each live range that is spilled,
 // this method allocate a new spill position on the stack.
 //----------------------------------------------------------------------------
@@ -1450,8 +1450,8 @@ void PhyRegAlloc::allocateRegisters()
   for (unsigned rc=0; rc < NumOfRegClasses ; rc++)  
     RegClassList[rc]->colorAllRegs();    
 
-  // Atter graph coloring, if some LRs did not receive a color (i.e, spilled)
-  // a poistion for such spilled LRs
+  // After graph coloring, if some LRs did not receive a color (i.e, spilled)
+  // a position for such spilled LRs
   //
   allocateStackSpace4SpilledLRs();
 
diff --git a/lib/CodeGen/RegAlloc/RegClass.cpp b/lib/CodeGen/RegAlloc/RegClass.cpp
index d4bd714..12582cc 100644
--- a/lib/CodeGen/RegAlloc/RegClass.cpp
+++ b/lib/CodeGen/RegAlloc/RegClass.cpp
@@ -93,7 +93,7 @@ void RegClass::pushAllIGNodes()
     //
     IGNodeSpill->pushOnStack(); 
    
-    // now push NON-constrined ones, if any
+    // now push NON-constrained ones, if any
     //
     NeedMoreSpills = !pushUnconstrainedIGNodes(); 
 
@@ -154,7 +154,7 @@ bool  RegClass::pushUnconstrainedIGNodes()
 
 
 //----------------------------------------------------------------------------
-// Get the IGNode withe the minimum spill cost
+// Get the IGNode with the minimum spill cost
 //----------------------------------------------------------------------------
 IGNode * RegClass::getIGNodeWithMinSpillCost()
 {
@@ -216,8 +216,8 @@ void RegClass::colorIGNode(IGNode *const Node)
       IGNode *NeighIGNode = Node->getAdjIGNode(n);
       LiveRange *NeighLR = NeighIGNode->getParentLR();
       
-      // Don't use a color if it is in use by the neighbour,
-      // or is suggested for use by the neighbour,
+      // Don't use a color if it is in use by the neighbor,
+      // or is suggested for use by the neighbor,
       // markColorsUsed() should be given the color and the reg type for
       // LR, not for NeighLR, because it should mark registers used based on
       // the type we are looking for, not on the regType for the neighbour.
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index f5334d5..6d1fd14 100644
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -886,7 +886,7 @@ void CWriter::printFunction(Function *F) {
     BasicBlock *Prev = BB->getPrev();
 
     // Don't print the label for the basic block if there are no uses, or if the
-    // only terminator use is the precessor basic block's terminator.  We have
+    // only terminator use is the predecessor basic block's terminator.  We have
     // to scan the use list because PHI nodes use basic blocks too but do not
     // require a label to be generated.
     //
@@ -1022,8 +1022,8 @@ void CWriter::printBranchToBlock(BasicBlock *CurBB, BasicBlock *Succ,
   }
 }
 
-// Brach instruction printing - Avoid printing out a brach to a basic block that
-// immediately succeeds the current one.
+// Branch instruction printing - Avoid printing out a branch to a basic block
+// that immediately succeeds the current one.
 //
 void CWriter::visitBranchInst(BranchInst &I) {
   if (I.isConditional()) {
@@ -1155,7 +1155,7 @@ void CWriter::visitCallInst(CallInst &I) {
 
       case LLVMIntrinsic::setjmp:
       case LLVMIntrinsic::sigsetjmp:
-        // This instrinsic should never exist in the program, but until we get
+        // This intrinsic should never exist in the program, but until we get
         // setjmp/longjmp transformations going on, we should codegen it to
         // something reasonable.  This will allow code that never calls longjmp
         // to work.
diff --git a/lib/Target/CBackend/Writer.cpp b/lib/Target/CBackend/Writer.cpp
index f5334d5..6d1fd14 100644
--- a/lib/Target/CBackend/Writer.cpp
+++ b/lib/Target/CBackend/Writer.cpp
@@ -886,7 +886,7 @@ void CWriter::printFunction(Function *F) {
     BasicBlock *Prev = BB->getPrev();
 
     // Don't print the label for the basic block if there are no uses, or if the
-    // only terminator use is the precessor basic block's terminator.  We have
+    // only terminator use is the predecessor basic block's terminator.  We have
     // to scan the use list because PHI nodes use basic blocks too but do not
     // require a label to be generated.
     //
@@ -1022,8 +1022,8 @@ void CWriter::printBranchToBlock(BasicBlock *CurBB, BasicBlock *Succ,
   }
 }
 
-// Brach instruction printing - Avoid printing out a brach to a basic block that
-// immediately succeeds the current one.
+// Branch instruction printing - Avoid printing out a branch to a basic block
+// that immediately succeeds the current one.
 //
 void CWriter::visitBranchInst(BranchInst &I) {
   if (I.isConditional()) {
@@ -1155,7 +1155,7 @@ void CWriter::visitCallInst(CallInst &I) {
 
       case LLVMIntrinsic::setjmp:
       case LLVMIntrinsic::sigsetjmp:
-        // This instrinsic should never exist in the program, but until we get
+        // This intrinsic should never exist in the program, but until we get
         // setjmp/longjmp transformations going on, we should codegen it to
         // something reasonable.  This will allow code that never calls longjmp
         // to work.
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 1e44e17..a04d4b8 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -104,7 +104,7 @@ PhyRegAlloc::~PhyRegAlloc() {
 } 
 
 //----------------------------------------------------------------------------
-// This method initally creates interference graphs (one in each reg class)
+// This method initially creates interference graphs (one in each reg class)
 // and IGNodeList (one in each IG). The actual nodes will be pushed later. 
 //----------------------------------------------------------------------------
 void PhyRegAlloc::createIGNodeListsAndIGs() {
@@ -145,7 +145,7 @@ void PhyRegAlloc::createIGNodeListsAndIGs() {
 
 //----------------------------------------------------------------------------
 // This method will add all interferences at for a given instruction.
-// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg 
+// Interference occurs only if the LR of Def (Inst or Arg) is of the same reg 
 // class as that of live var. The live var passed to this function is the 
 // LVset AFTER the instruction
 //----------------------------------------------------------------------------
@@ -290,9 +290,9 @@ void PhyRegAlloc::buildInterferenceGraphs()
       bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
 
       if (isCallInst ) {
-	// set the isCallInterference flag of each live range wich extends
-	// accross this call instruction. This information is used by graph
-	// coloring algo to avoid allocating volatile colors to live ranges
+	// set the isCallInterference flag of each live range which extends
+	// across this call instruction. This information is used by graph
+	// coloring algorithm to avoid allocating volatile colors to live ranges
 	// that span across calls (since they have to be saved/restored)
 	//
 	setCallInterferences(MInst, &LVSetAI);
@@ -331,7 +331,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
   } // for all BBs in function
 
 
-  // add interferences for function arguments. Since there are no explict 
+  // add interferences for function arguments. Since there are no explicit 
   // defs in the function for args, we have to add them manually
   //  
   addInterferencesForArgs();          
@@ -343,7 +343,7 @@ void PhyRegAlloc::buildInterferenceGraphs()
 
 
 //--------------------------------------------------------------------------
-// Pseudo instructions will be exapnded to multiple instructions by the
+// Pseudo-instructions will be expanded to multiple instructions by the
 // assembler. Consequently, all the opernds must get distinct registers.
 // Therefore, we mark all operands of a pseudo instruction as they interfere
 // with one another.
@@ -404,7 +404,7 @@ void PhyRegAlloc::addInterferencesForArgs() {
 
 //----------------------------------------------------------------------------
 // This method is called after register allocation is complete to set the
-// allocated reisters in the machine code. This code will add register numbers
+// allocated registers in the machine code. This code will add register numbers
 // to MachineOperands that contain a Value. Also it calls target specific
 // methods to produce caller saving instructions. At the end, it adds all
 // additional instructions produced by the register allocator to the 
@@ -722,7 +722,7 @@ void PhyRegAlloc::updateMachineCode()
 // if it contains many spilled operands. Each time it is called, it finds
 // a register which is not live at that instruction and also which is not
 // used by other spilled operands of the same instruction. Then it uses
-// this register temporarily to accomodate the spilled value.
+// this register temporarily to accommodate the spilled value.
 //----------------------------------------------------------------------------
 
 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR, 
@@ -835,7 +835,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
 
 
 //----------------------------------------------------------------------------
-// This method inserts caller saving/restoring instructons before/after
+// This method inserts caller saving/restoring instructions before/after
 // a call machine instruction. The caller saving/restoring instructions are
 // inserted like:
 //    ** caller saving instructions
@@ -1077,7 +1077,7 @@ int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
 
 //----------------------------------------------------------------------------
 // This method is called to get a new unused register that can be used
-// to accomodate a temporary value.  This method may be called several times
+// to accommodate a temporary value.  This method may be called several times
 // for a single machine instruction.  Each time it is called, it finds a
 // register which is not live at that instruction and also which is not used
 // by other spilled operands of the same instruction.  Return register number
@@ -1370,7 +1370,7 @@ void PhyRegAlloc::markUnusableSugColors()
 
 //----------------------------------------------------------------------------
 // The following method will set the stack offsets of the live ranges that
-// are decided to be spillled. This must be called just after coloring the
+// are decided to be spilled. This must be called just after coloring the
 // LRs using the graph coloring algo. For each live range that is spilled,
 // this method allocate a new spill position on the stack.
 //----------------------------------------------------------------------------
@@ -1450,8 +1450,8 @@ void PhyRegAlloc::allocateRegisters()
   for (unsigned rc=0; rc < NumOfRegClasses ; rc++)  
     RegClassList[rc]->colorAllRegs();    
 
-  // Atter graph coloring, if some LRs did not receive a color (i.e, spilled)
-  // a poistion for such spilled LRs
+  // After graph coloring, if some LRs did not receive a color (i.e, spilled)
+  // a position for such spilled LRs
   //
   allocateStackSpace4SpilledLRs();
 
diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp
index d4bd714..12582cc 100644
--- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp
+++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp
@@ -93,7 +93,7 @@ void RegClass::pushAllIGNodes()
     //
     IGNodeSpill->pushOnStack(); 
    
-    // now push NON-constrined ones, if any
+    // now push NON-constrained ones, if any
     //
     NeedMoreSpills = !pushUnconstrainedIGNodes(); 
 
@@ -154,7 +154,7 @@ bool  RegClass::pushUnconstrainedIGNodes()
 
 
 //----------------------------------------------------------------------------
-// Get the IGNode withe the minimum spill cost
+// Get the IGNode with the minimum spill cost
 //----------------------------------------------------------------------------
 IGNode * RegClass::getIGNodeWithMinSpillCost()
 {
@@ -216,8 +216,8 @@ void RegClass::colorIGNode(IGNode *const Node)
       IGNode *NeighIGNode = Node->getAdjIGNode(n);
       LiveRange *NeighLR = NeighIGNode->getParentLR();
       
-      // Don't use a color if it is in use by the neighbour,
-      // or is suggested for use by the neighbour,
+      // Don't use a color if it is in use by the neighbor,
+      // or is suggested for use by the neighbor,
       // markColorsUsed() should be given the color and the reg type for
       // LR, not for NeighLR, because it should mark registers used based on
       // the type we are looking for, not on the regType for the neighbour.