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authorEvan Cheng <evan.cheng@apple.com>2009-11-03 05:50:57 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-11-03 05:50:57 +0000
commit3f4e47be0a9b26501baf0ea0017795ffb2e79fc1 (patch)
treec778eee2691d7dfd850a15d5635f85c87d630925 /lib
parentff2f6831434c586a00d8b63c8434bf24d1300e9a (diff)
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Add QPR_8 as a superreg class of SPR_8 and DPR_8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85869 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.td7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index 7d6b0bb..d393e8d 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -357,6 +357,13 @@ def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
let SubRegClassList = [SPR, SPR, SPR, SPR, DPR_VFP2, DPR_VFP2];
}
+// Subset of QPR that have DPR_8 and SPR_8 subregs.
+def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
+ 128,
+ [Q0, Q1, Q2, Q3]> {
+ let SubRegClassList = [SPR_8, SPR_8, SPR_8, SPR_8, DPR_8, DPR_8];
+}
+
// Condition code registers.
def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>;