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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-11 20:41:13 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-11 20:41:13 +0000 |
| commit | 45251b370733b167d1d0640a027365f7208f7d10 (patch) | |
| tree | afb874fb220ca4a97f2339847b1335b49e8e8a71 /lib | |
| parent | 9fe72bcd3714d136b371aa85d293e16363c29914 (diff) | |
| download | external_llvm-45251b370733b167d1d0640a027365f7208f7d10.zip external_llvm-45251b370733b167d1d0640a027365f7208f7d10.tar.gz external_llvm-45251b370733b167d1d0640a027365f7208f7d10.tar.bz2 | |
Tidy up. Remove unused template parameter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137345 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 20 |
2 files changed, 11 insertions, 11 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 343dee55..eb613cd 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -591,7 +591,7 @@ class AI3ld<bits<4> op, bit op20, dag oops, dag iops, Format f, let DecoderMethod = "DecodeAddrMode3Instruction"; } -class AI3ldstidx<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops, +class AI3ldstidx<bits<4> op, bit op20, bit isPre, dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string opc, string asm, string cstr, list<dag> pattern> : I<oops, iops, AddrMode3, 4, im, f, itin, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index df86d12..2b7fac2 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2058,8 +2058,8 @@ defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>; defm LDRB : AI2_ldridx<1, "ldrb", IIC_iLoad_bh_ru>; } -multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> { - def _PRE : AI3ldstidx<op, op20, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), +multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> { + def _PRE : AI3ldstidx<op, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins addrmode3:$addr), IndexModePre, LdMiscFrm, itin, opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> { @@ -2071,7 +2071,7 @@ multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> { let Inst{3-0} = addr{3-0}; // imm3_0/Rm let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3"; } - def _POST : AI3ldstidx<op, op20, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), + def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), (ins addr_offset_none:$addr, am3offset:$offset), IndexModePost, LdMiscFrm, itin, opc, "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", @@ -2087,11 +2087,11 @@ multiclass AI3_ldridx<bits<4> op, bit op20, string opc, InstrItinClass itin> { } let mayLoad = 1, neverHasSideEffects = 1 in { -defm LDRH : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>; -defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>; -defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>; +defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>; +defm LDRSH : AI3_ldridx<0b1111, "ldrsh", IIC_iLoad_bh_ru>; +defm LDRSB : AI3_ldridx<0b1101, "ldrsb", IIC_iLoad_bh_ru>; let hasExtraDefRegAllocReq = 1 in { -def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), +def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), (ins addrmode3:$addr), IndexModePre, LdMiscFrm, IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr!", @@ -2105,7 +2105,7 @@ def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), let DecoderMethod = "DecodeAddrMode3Instruction"; let AsmMatchConverter = "cvtLdrdPre"; } -def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), +def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb), (ins addr_offset_none:$addr, am3offset:$offset), IndexModePost, LdMiscFrm, IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr, $offset", @@ -2370,7 +2370,7 @@ def STRH_POST: AI3stridx<0b1011, 0, 0, (outs GPR:$Rn_wb), GPR:$Rn, am3offset:$offset))]>; let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { -def STRD_PRE : AI3ldstidx<0b1111, 0, 1, 1, (outs GPR:$Rn_wb), +def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr), IndexModePre, StMiscFrm, IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", @@ -2385,7 +2385,7 @@ def STRD_PRE : AI3ldstidx<0b1111, 0, 1, 1, (outs GPR:$Rn_wb), let AsmMatchConverter = "cvtStrdPre"; } -def STRD_POST: AI3ldstidx<0b1111, 0, 1, 0, (outs GPR:$Rn_wb), +def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr, am3offset:$offset), IndexModePost, StMiscFrm, IIC_iStore_d_ru, |