diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2008-07-21 06:34:17 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-07-21 06:34:17 +0000 |
| commit | 47906a2962c3547a41752fd09fae7176788c30e1 (patch) | |
| tree | f77dac4640fe4aa7a14b08d1fc70c4e5a7b1b7ea /lib | |
| parent | bef92abc5d5a5a2826d4b764be1ddb229a12f824 (diff) | |
| download | external_llvm-47906a2962c3547a41752fd09fae7176788c30e1.zip external_llvm-47906a2962c3547a41752fd09fae7176788c30e1.tar.gz external_llvm-47906a2962c3547a41752fd09fae7176788c30e1.tar.bz2 | |
Use movaps instead of movups to spill 16-byte vector values when default alignment is >= 16. This fixes some massive performance regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53844 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index d603ee3..8cf268e 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -1739,7 +1739,9 @@ void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC) const { const MachineFunction &MF = *MBB.getParent(); - unsigned Opc = getStoreRegOpcode(RC, RI.needsStackRealignment(MF)); + bool isAligned = (RI.getStackAlignment() >= 16) || + RI.needsStackRealignment(MF); + unsigned Opc = getStoreRegOpcode(RC, isAligned); addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx) .addReg(SrcReg, false, false, isKill); } @@ -1749,7 +1751,9 @@ void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - unsigned Opc = getStoreRegOpcode(RC, RI.needsStackRealignment(MF)); + bool isAligned = (RI.getStackAlignment() >= 16) || + RI.needsStackRealignment(MF); + unsigned Opc = getStoreRegOpcode(RC, isAligned); MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); @@ -1800,7 +1804,9 @@ void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC) const{ const MachineFunction &MF = *MBB.getParent(); - unsigned Opc = getLoadRegOpcode(RC, RI.needsStackRealignment(MF)); + bool isAligned = (RI.getStackAlignment() >= 16) || + RI.needsStackRealignment(MF); + unsigned Opc = getLoadRegOpcode(RC, isAligned); addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx); } @@ -1808,7 +1814,9 @@ void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - unsigned Opc = getLoadRegOpcode(RC, RI.needsStackRealignment(MF)); + bool isAligned = (RI.getStackAlignment() >= 16) || + RI.needsStackRealignment(MF); + unsigned Opc = getLoadRegOpcode(RC, isAligned); MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) MIB = X86InstrAddOperand(MIB, Addr[i]); @@ -2275,7 +2283,9 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, const MachineFunction &MF = DAG.getMachineFunction(); if (FoldedLoad) { MVT VT = *RC->vt_begin(); - Load = DAG.getTargetNode(getLoadRegOpcode(RC, RI.needsStackRealignment(MF)), + bool isAligned = (RI.getStackAlignment() >= 16) || + RI.needsStackRealignment(MF); + Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), VT, MVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Load); @@ -2306,10 +2316,10 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, AddrOps.pop_back(); AddrOps.push_back(SDOperand(NewNode, 0)); AddrOps.push_back(Chain); - SDNode *Store = - DAG.getTargetNode(getStoreRegOpcode(DstRC, - RI.needsStackRealignment(MF)), - MVT::Other, &AddrOps[0], AddrOps.size()); + bool isAligned = (RI.getStackAlignment() >= 16) || + RI.needsStackRealignment(MF); + SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), + MVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Store); } |