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authorOwen Anderson <resistor@mac.com>2010-12-15 18:48:27 +0000
committerOwen Anderson <resistor@mac.com>2010-12-15 18:48:27 +0000
commit47dbd429daefa9b3f19347194ddfb6f69642465e (patch)
tree49cd641d22462d0648d5a3e7567c89a0c20057a1 /lib
parent49e41c517966af290a6115bbc57878f1033ad1e9 (diff)
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Implement cleanups suggested by Daniel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121875 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/MC/MCAssembler.cpp18
-rw-r--r--lib/Target/ARM/ARMMCCodeEmitter.cpp8
2 files changed, 15 insertions, 11 deletions
diff --git a/lib/MC/MCAssembler.cpp b/lib/MC/MCAssembler.cpp
index 0fbd77c..0d114fb 100644
--- a/lib/MC/MCAssembler.cpp
+++ b/lib/MC/MCAssembler.cpp
@@ -248,14 +248,18 @@ bool MCAssembler::EvaluateFixup(const MCObjectWriter &Writer,
if (IsResolved)
IsResolved = Writer.IsFixupFullyResolved(*this, Target, IsPCRel, DF);
+ bool ShouldAlignPC = Emitter.getFixupKindInfo(Fixup.getKind()).Flags &
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits;
+ assert((ShouldAlignPC ? IsPCRel : true) &&
+ "FKF_IsAlignedDownTo32Bits is only allowed on PC-relative fixups!");
+
if (IsPCRel) {
- bool ShouldAlignPC = Emitter.getFixupKindInfo(
- Fixup.getKind()).Flags & MCFixupKindInfo::FKF_IsAligned;
- // PC should be aligned to a 4-byte value.
- if (ShouldAlignPC)
- Value -= Layout.getFragmentOffset(DF) + (Fixup.getOffset() & ~0x3);
- else
- Value -= Layout.getFragmentOffset(DF) + Fixup.getOffset();
+ uint32_t Offset = Fixup.getOffset();
+
+ // A number of ARM fixups in Thumb mode require that the effective PC
+ // address be determined as the 32-bit aligned version of the actual offset.
+ if (ShouldAlignPC) Offset &= 0x3;
+ Value -= Layout.getFragmentOffset(DF) + Offset;
}
// ARM fixups based from a thumb function address need to have the low
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index db68f35..1efcae0 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -51,15 +51,15 @@ public:
// Name Offset (bits) Size (bits) Flags
{ "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAligned},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAligned},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAligned},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAligned},
+ MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
{ "fixup_arm_branch", 0, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },