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authorJim Grosbach <grosbach@apple.com>2008-10-03 15:53:56 +0000
committerJim Grosbach <grosbach@apple.com>2008-10-03 15:53:56 +0000
commit48b828fdb467655fa630fed41e49e2a481fb6dab (patch)
treea3ec81e111f256399d0b6a85eea8aeb3df3b50b1 /lib
parent016d34cc4caa5eac50378c652a5301fb1fbd48b3 (diff)
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Indexing off by one resulted in errant encoding of source register for
reg->reg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57011 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/ARMCodeEmitter.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 3936afc..a8fe2ea 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -416,7 +416,7 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
const MachineOperand &MO = MI.getOperand(OpIdx);
if (MO.isReg())
// Encode register Rm.
- return Binary | getMachineOpValue(MI, NumDefs + 1);
+ return Binary | getMachineOpValue(MI, NumDefs);
// Encode so_imm.
// Set bit I(25) to identify this is the immediate form of <shifter_op>