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| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-10-31 18:37:55 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-10-31 18:37:55 +0000 |
| commit | 497204a94b6ebe94b0cc9b9ef11eee7baf1df53b (patch) | |
| tree | 65cace6203c0e12c77a630fbf7decd274b942de5 /lib | |
| parent | b586aae15edfec655ca0d950776e92cab66516b6 (diff) | |
| download | external_llvm-497204a94b6ebe94b0cc9b9ef11eee7baf1df53b.zip external_llvm-497204a94b6ebe94b0cc9b9ef11eee7baf1df53b.tar.gz external_llvm-497204a94b6ebe94b0cc9b9ef11eee7baf1df53b.tar.bz2 | |
[mips] Set isAsCheapAsAMove flag on ADDiu and DADDiu, which enables
re-materialization of immediate loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167153 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 7 |
2 files changed, 7 insertions, 2 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index ed0ea0e..a611168 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -86,7 +86,7 @@ let DecoderNamespace = "Mips64" in { def DADDi : ArithOverflowI<0x18, "daddi", add, simm16_64, immSExt16, CPU64Regs>; def DADDiu : ArithLogicI<0x19, "daddiu", add, simm16_64, immSExt16, - CPU64Regs>; + CPU64Regs>, IsAsCheapAsAMove; def DANDi : ArithLogicI<0x0c, "andi", and, uimm16_64, immZExt16, CPU64Regs>; def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index cc216c3..3f6cebd 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -200,6 +200,10 @@ class IsTailCall { bit isCodeGenOnly = 1; } +class IsAsCheapAsAMove { + bit isAsCheapAsAMove = 1; +} + //===----------------------------------------------------------------------===// // Instruction format superclass //===----------------------------------------------------------------------===// @@ -925,7 +929,8 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; //===----------------------------------------------------------------------===// /// Arithmetic Instructions (ALU Immediate) -def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>; +def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>, + IsAsCheapAsAMove; def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; |