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| author | Cameron Zwarich <zwarich@apple.com> | 2011-04-13 21:01:19 +0000 |
|---|---|---|
| committer | Cameron Zwarich <zwarich@apple.com> | 2011-04-13 21:01:19 +0000 |
| commit | 5af60ce2a8d4dc820664c9dc5fbbcff428402c15 (patch) | |
| tree | 00899a425cf99568135a5dcc5c115b4ebbf969f4 /lib | |
| parent | 8b505739f4a50916261a4624ed067d6923cc43a9 (diff) | |
| download | external_llvm-5af60ce2a8d4dc820664c9dc5fbbcff428402c15.zip external_llvm-5af60ce2a8d4dc820664c9dc5fbbcff428402c15.tar.gz external_llvm-5af60ce2a8d4dc820664c9dc5fbbcff428402c15.tar.bz2 | |
Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 563b37e..d5f65c7 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5474,7 +5474,7 @@ static SDValue PerformORCombine(SDNode *N, EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, N0->getOperand(1), N0->getOperand(0), - N1->getOperand(1)); + N1->getOperand(0)); return DAG.getNode(ISD::BITCAST, dl, VT, Result); } } |