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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-22 12:39:25 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-22 12:39:25 +0000 |
| commit | 5b2bba61229fb8c262be90ef7705b41cb29edde0 (patch) | |
| tree | e742905e9d0e09e38f13957069e4229d68f074eb /lib | |
| parent | b8dcb314f7f9c5c0f068a322c689a64881d78b70 (diff) | |
| download | external_llvm-5b2bba61229fb8c262be90ef7705b41cb29edde0.zip external_llvm-5b2bba61229fb8c262be90ef7705b41cb29edde0.tar.gz external_llvm-5b2bba61229fb8c262be90ef7705b41cb29edde0.tar.bz2 | |
Fix pr11193.
SHL inserts zeros from the right, thus even when the original
sign_extend_inreg value was of 1-bit, we need to sra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142724 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 96f04e7..7dec7c4 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -10146,9 +10146,6 @@ SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) DAG.getConstant(SHLIntrinsicsID, MVT::i32), Node->getOperand(0), ShAmt); - // In case of 1 bit sext, no need to shr - if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, DAG.getConstant(SRAIntrinsicsID, MVT::i32), Tmp1, ShAmt); |