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| author | Craig Topper <craig.topper@gmail.com> | 2013-08-21 05:57:45 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-08-21 05:57:45 +0000 |
| commit | 5bdf397e25bf0e5a6473f44d49a04e8ff184c442 (patch) | |
| tree | 7bfeb291cde0483a9053d5ded942288f3e7a0070 /lib | |
| parent | ec7b5e9290bc0e1b266525a4757773e9ab87847e (diff) | |
| download | external_llvm-5bdf397e25bf0e5a6473f44d49a04e8ff184c442.zip external_llvm-5bdf397e25bf0e5a6473f44d49a04e8ff184c442.tar.gz external_llvm-5bdf397e25bf0e5a6473f44d49a04e8ff184c442.tar.bz2 | |
Synchronize VEX JIT encoding code with the MCJIT version. Fix a bug in the MCJIT code where CurOp was being incremented even if the operand it was pointing at wasn't used. Maybe only matters if there are any EVEX_K instructions that aren't VEX_4V.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188868 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 21 |
2 files changed, 11 insertions, 12 deletions
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 8515879..7173d51 100644 --- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -786,8 +786,8 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, VEX_4V = getVEXRegisterEncoding(MI, CurOp); if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg())) EVEX_V2 = 0x0; + CurOp++; } - CurOp++; if (HasEVEX_K) EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++); diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 0f9c562..e786ebb 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -982,16 +982,13 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags, // FMA4: // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(VEX_I8IMM) // dst(ModR/M.reg), src1(VEX_4V), src2(VEX_I8IMM), src3(ModR/M), - if (X86II::isX86_64ExtendedReg(MI.getOperand(0).getReg())) + if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) VEX_R = 0x0; + CurOp++; if (HasVEX_4V) { - if (HasMemOp4) - VEX_4V = getVEXRegisterEncoding(MI, 1); - else - // FMA3 instructions operands are dst, src1, src2, src3 - // dst and src1 are the same and not encoded separately - VEX_4V = getVEXRegisterEncoding(MI, 2); + VEX_4V = getVEXRegisterEncoding(MI, CurOp); + CurOp++; } if (X86II::isX86_64ExtendedReg( @@ -1002,7 +999,7 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags, VEX_X = 0x0; if (HasVEX_4VOp3) - VEX_4V = getVEXRegisterEncoding(MI, X86::AddrNumOperands+1); + VEX_4V = getVEXRegisterEncoding(MI, CurOp+X86::AddrNumOperands); break; case X86II::MRM0m: case X86II::MRM1m: case X86II::MRM2m: case X86II::MRM3m: @@ -1012,7 +1009,7 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags, // MemAddr // src1(VEX_4V), MemAddr if (HasVEX_4V) - VEX_4V = getVEXRegisterEncoding(MI, 0); + VEX_4V = getVEXRegisterEncoding(MI, CurOp++); if (X86II::isX86_64ExtendedReg( MI.getOperand(MemOperand+X86::AddrBaseReg).getReg())) @@ -1065,8 +1062,10 @@ void Emitter<CodeEmitter>::emitVEXOpcodePrefix(uint64_t TSFlags, case X86II::MRM6r: case X86II::MRM7r: // MRM0r-MRM7r instructions forms: // dst(VEX_4V), src(ModR/M), imm8 - VEX_4V = getVEXRegisterEncoding(MI, 0); - if (X86II::isX86_64ExtendedReg(MI.getOperand(1).getReg())) + VEX_4V = getVEXRegisterEncoding(MI, CurOp); + CurOp++; + + if (X86II::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg())) VEX_B = 0x0; break; default: // RawFrm |