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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-12-01 17:48:51 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-12-01 17:48:51 +0000 |
| commit | 6251b36d88b4cb5b256b67f3cd885f2f61f57d54 (patch) | |
| tree | f3b0e44ba14598df8250aaba376dd302e7a919bf /lib | |
| parent | 6510b22cec7de4f0acc9965ec24c3668a6a8a87e (diff) | |
| download | external_llvm-6251b36d88b4cb5b256b67f3cd885f2f61f57d54.zip external_llvm-6251b36d88b4cb5b256b67f3cd885f2f61f57d54.tar.gz external_llvm-6251b36d88b4cb5b256b67f3cd885f2f61f57d54.tar.bz2 | |
major think-o
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24564 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 5423393..44b3828 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1538,23 +1538,28 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { return Result; case AlphaISD::CVTQT_: - BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CVTQT, 1, Result).addReg(Tmp1); return Result; case AlphaISD::CVTQS_: - BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CVTQS, 1, Result).addReg(Tmp1); return Result; case AlphaISD::CVTTQ_: - BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::CVTTQ, 1, Result).addReg(Tmp1); return Result; case AlphaISD::ITOFT_: - BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::ITOFT, 1, Result).addReg(Tmp1); return Result; case AlphaISD::FTOIT_: - BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(SelectExpr(N.getOperand(0))); + Tmp1 = SelectExpr(N.getOperand(0)); + BuildMI(BB, Alpha::FTOIT, 1, Result).addReg(Tmp1); return Result; case ISD::AssertSext: |