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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-07-12 18:10:18 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-07-12 18:10:18 +0000 |
commit | 635c9f0fbddb5aef75870f379522b9f279b77385 (patch) | |
tree | 27fce915f324dcf655f34868b26353c59c565711 /lib | |
parent | f90244488d1e1ac608a9272ecb1d5950902234c6 (diff) | |
download | external_llvm-635c9f0fbddb5aef75870f379522b9f279b77385.zip external_llvm-635c9f0fbddb5aef75870f379522b9f279b77385.tar.gz external_llvm-635c9f0fbddb5aef75870f379522b9f279b77385.tar.bz2 |
Implement support for promotion of AND/OR/XOR on integer types.
The blackfin processor has a legal i16 type, but only logic operations on i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75419 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 315f043..a40a0c3 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3022,16 +3022,26 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node, break; case ISD::AND: case ISD::OR: - case ISD::XOR: - assert(OVT.isVector() && "Don't know how to promote scalar logic ops"); - // Bit convert each of the values to the new type. - Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0)); - Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1)); + case ISD::XOR: { + unsigned ExtOp, TruncOp; + if (OVT.isVector()) { + ExtOp = ISD::BIT_CONVERT; + TruncOp = ISD::BIT_CONVERT; + } else if (OVT.isInteger()) { + ExtOp = ISD::ANY_EXTEND; + TruncOp = ISD::TRUNCATE; + } else { + llvm_report_error("Cannot promote logic operation"); + } + // Promote each of the values to the new type. + Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); + Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); + // Perform the larger operation, then convert back Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); - // Bit convert the result back the original type. - Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1)); + Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); break; - case ISD::SELECT: + } + case ISD::SELECT: { unsigned ExtOp, TruncOp; if (Node->getValueType(0).isVector()) { ExtOp = ISD::BIT_CONVERT; @@ -3056,6 +3066,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node, DAG.getIntPtrConstant(0)); Results.push_back(Tmp1); break; + } case ISD::VECTOR_SHUFFLE: { SmallVector<int, 8> Mask; cast<ShuffleVectorSDNode>(Node)->getMask(Mask); |