Final de-tabification.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 111 insertions, 112 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index d8230be..b316d41 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -134,7 +134,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
     if (G && R->getReg() != 0 &&
         TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
       Op = Op + " " +
-	G->getTarget().getRegisterInfo()->getName(R->getReg());
+        G->getTarget().getRegisterInfo()->getName(R->getReg());
     } else {
       Op += " #" + utostr(R->getReg());
     }
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 2e2dc5b..d210d93 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -1262,7 +1262,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
           else
             DOUT << "Reusing SS#" << ReuseSlot;
           DOUT << " from physreg " << TRI->getName(PhysReg)
-	       << " for vreg" << VirtReg
+               << " for vreg" << VirtReg
                << " instead of reloading into same physreg.\n";
           unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
           MI.getOperand(i).setReg(RReg);
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index d3bce5d..49cf624 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -46,9 +46,9 @@ def ARMWrapper       : SDNode<"ARMISD::Wrapper",     SDTIntUnaryOp>;
 def ARMWrapperJT     : SDNode<"ARMISD::WrapperJT",   SDTIntBinOp>;
 
 def ARMcallseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeqStart,
-    		              [SDNPHasChain, SDNPOutFlag]>;
+                              [SDNPHasChain, SDNPOutFlag]>;
 def ARMcallseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_ARMCallSeqEnd,
-    		              [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+                              [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 def ARMcall          : SDNode<"ARMISD::CALL", SDT_ARMcall,
                               [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td
index 19a8460..1769ec2 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.td
+++ b/lib/Target/Alpha/AlphaInstrInfo.td
@@ -27,7 +27,7 @@ def Alpha_gprelhi : SDNode<"AlphaISD::GPRelHi",   SDTIntBinOp, []>;
 def Alpha_rellit  : SDNode<"AlphaISD::RelLit",    SDTIntBinOp, [SDNPMayLoad]>;
 
 def retflag       : SDNode<"AlphaISD::RET_FLAG", SDTNone,
-	                   [SDNPHasChain, SDNPOptInFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag]>;
 
 // These are target-independent nodes, but have target-specific formats.
 def SDT_AlphaCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i64> ]>;
@@ -35,7 +35,7 @@ def SDT_AlphaCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i64>,
                                            SDTCisVT<1, i64> ]>;
 
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_AlphaCallSeqStart,
-    		           [SDNPHasChain, SDNPOutFlag]>;
+                           [SDNPHasChain, SDNPOutFlag]>;
 def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_AlphaCallSeqEnd,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
@@ -450,21 +450,21 @@ def LDWUr : MForm<0x0C, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
 
 let OutOperandList = (ops), InOperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
 def STB   : MForm<0x0E, 0, "stb $RA,$DISP($RB)",
-		 [(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
+                 [(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
 def STBr  : MForm<0x0E, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
-		 [(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
+                 [(truncstorei8 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
 def STW   : MForm<0x0D, 0, "stw $RA,$DISP($RB)",
-		 [(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
+                 [(truncstorei16 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
 def STWr  : MForm<0x0D, 0, "stw $RA,$DISP($RB)\t\t!gprellow",
-		 [(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
+                 [(truncstorei16 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
 def STL   : MForm<0x2C, 0, "stl $RA,$DISP($RB)",
-		 [(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
+                 [(truncstorei32 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
 def STLr  : MForm<0x2C, 0, "stl $RA,$DISP($RB)\t\t!gprellow",
-		 [(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
+                 [(truncstorei32 GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
 def STQ   : MForm<0x2D, 0, "stq $RA,$DISP($RB)",
-		 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
+                 [(store GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_ist>;
 def STQr  : MForm<0x2D, 0, "stq $RA,$DISP($RB)\t\t!gprellow",
-		 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
+                 [(store GPRC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_ist>;
 }
 
 //Load address
@@ -481,27 +481,27 @@ def LDAHr : MForm<0x09, 0, "ldah $RA,$DISP($RB)\t\t!gprelhigh",
 
 let OutOperandList = (ops), InOperandList = (ops F4RC:$RA, s64imm:$DISP, GPRC:$RB) in {
 def STS  : MForm<0x26, 0, "sts $RA,$DISP($RB)",
-		[(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
+                [(store F4RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
 def STSr : MForm<0x26, 0, "sts $RA,$DISP($RB)\t\t!gprellow",
-		[(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
+                [(store F4RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
 }
 let OutOperandList = (ops F4RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
 def LDS  : MForm<0x22, 1, "lds $RA,$DISP($RB)",
-		[(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
+                [(set F4RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
 def LDSr : MForm<0x22, 1, "lds $RA,$DISP($RB)\t\t!gprellow",
-		[(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
+                [(set F4RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
 }
 let OutOperandList = (ops), InOperandList = (ops F8RC:$RA, s64imm:$DISP, GPRC:$RB) in {
 def STT  : MForm<0x27, 0, "stt $RA,$DISP($RB)",
-		[(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
+                 [(store F8RC:$RA, (add GPRC:$RB, immSExt16:$DISP))], s_fst>;
 def STTr : MForm<0x27, 0, "stt $RA,$DISP($RB)\t\t!gprellow",
-		[(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
+                 [(store F8RC:$RA, (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB))], s_fst>;
 }
 let OutOperandList = (ops F8RC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in {
 def LDT  : MForm<0x23, 1, "ldt $RA,$DISP($RB)",
-		[(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
+                [(set F8RC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))], s_fld>;
 def LDTr : MForm<0x23, 1, "ldt $RA,$DISP($RB)\t\t!gprellow",
-		[(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
+                [(set F8RC:$RA, (load (Alpha_gprello tglobaladdr:$DISP, GPRC:$RB)))], s_fld>;
 }
 
 
diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index c8cdf2e..0fa63ff 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -23,7 +23,7 @@ def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
 
 def SDT_IA64RetFlag : SDTypeProfile<0, 0, []>;
 def retflag         : SDNode<"IA64ISD::RET_FLAG", SDT_IA64RetFlag,
-	                   [SDNPHasChain, SDNPOptInFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag]>;
 
 //===---------
 // Instruction types
@@ -115,36 +115,36 @@ def imm64  : PatLeaf<(i64 imm)>;
 
 def ADD  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "add $dst = $src1, $src2",
-	   [(set GR:$dst, (add GR:$src1, GR:$src2))]>, isA;
+           [(set GR:$dst, (add GR:$src1, GR:$src2))]>, isA;
 
 def ADD1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "add $dst = $src1, $src2, 1",
-	   [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>, isA;
+           [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>, isA;
 
 def ADDS : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
            "adds $dst = $imm, $src1",
-	   [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>, isA;
+           [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>, isA;
  
 def MOVL : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm),
            "movl $dst = $imm",
-	   [(set GR:$dst, imm64:$imm)]>, isLX;
+           [(set GR:$dst, imm64:$imm)]>, isLX;
 
 def ADDL_GA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, globaladdress:$imm),
            "addl $dst = $imm, $src1",
-	   []>, isA;
+           []>, isA;
 
 // hmm 
 def ADDL_EA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, calltarget:$imm),
            "addl $dst = $imm, $src1",
-	   []>, isA;
+           []>, isA;
  
 def SUB  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2",
-	   [(set GR:$dst, (sub GR:$src1, GR:$src2))]>, isA;
+           [(set GR:$dst, (sub GR:$src1, GR:$src2))]>, isA;
 
 def SUB1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2, 1",
-	   [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>, isA;
+           [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>, isA;
 
 let isTwoAddress = 1 in {
 def TPCADDIMM22 : AForm<0x03, 0x0b,
@@ -182,33 +182,33 @@ def ZXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt4 $dst = $sr
 // fixme: shrs vs shru?
 def MIX1L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix1.l $dst = $src1, $src2",
-	  [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
-	                     (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>, isI;
+          [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
+                          (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>, isI;
 
 def MIX2L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix2.l $dst = $src1, $src2",
-	  [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
-	                     (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>, isI;
+          [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
+                          (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>, isI;
 
 def MIX4L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix4.l $dst = $src1, $src2",
-	  [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
-	                     (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>, isI;
+          [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
+                          (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>, isI;
 
 def MIX1R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix1.r $dst = $src1, $src2",
-	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
-	                     (and GR:$src2, isMIX1Rable)))]>, isI;
+          [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
+                          (and GR:$src2, isMIX1Rable)))]>, isI;
 
 def MIX2R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix2.r $dst = $src1, $src2",
-	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
-	                     (and GR:$src2, isMIX2Rable)))]>, isI;
+          [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
+                          (and GR:$src2, isMIX2Rable)))]>, isI;
 
 def MIX4R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "mix4.r $dst = $src1, $src2",
-	  [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
-	                     (and GR:$src2, isMIX4Rable)))]>, isI;
+          [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
+                          (and GR:$src2, isMIX4Rable)))]>, isI;
 
 def GETFSIGD : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
   "getf.sig $dst = $src",
@@ -244,14 +244,14 @@ def : Pat<(mulhu GR:$src1, GR:$src2),
 
 def AND   : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "and $dst = $src1, $src2",
-	  [(set GR:$dst, (and GR:$src1, GR:$src2))]>, isA;
+          [(set GR:$dst, (and GR:$src1, GR:$src2))]>, isA;
 def ANDCM : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "andcm $dst = $src1, $src2",
-	  [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>, isA;
+          [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>, isA;
 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
 def OR    : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "or $dst = $src1, $src2",
-	  [(set GR:$dst, (or GR:$src1, GR:$src2))]>, isA;
+          [(set GR:$dst, (or GR:$src1, GR:$src2))]>, isA;
 
 def pOR   : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
           "($qp) or $dst = $src1, $src2">, isA;
@@ -260,34 +260,34 @@ def pOR   : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
 // of the compare!
 def CMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.eq $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>, isA;
 def CMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.gt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>, isA;
 def CMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.ge $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setge GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setge GR:$src1, GR:$src2))]>, isA;
 def CMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.lt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>, isA;
 def CMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.le $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setle GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setle GR:$src1, GR:$src2))]>, isA;
 def CMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.ne $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setne GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setne GR:$src1, GR:$src2))]>, isA;
 def CMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.ltu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setult GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setult GR:$src1, GR:$src2))]>, isA;
 def CMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.gtu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>, isA;
 def CMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.leu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setule GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setule GR:$src1, GR:$src2))]>, isA;
 def CMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
           "cmp.geu $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>, isA;
+          [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>, isA;
 
 // and we do the whole thing again for FP compares!
 def FCMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
@@ -295,38 +295,38 @@ def FCMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>, isF;
 def FCMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.gt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>, isF;
 def FCMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.ge $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setge FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setge FP:$src1, FP:$src2))]>, isF;
 def FCMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.lt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>, isF;
 def FCMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.le $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setle FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setle FP:$src1, FP:$src2))]>, isF;
 def FCMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.neq $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF;
 def FCMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.lt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF;
 def FCMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.gt $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF;
 def FCMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.le $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF;
 def FCMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
           "fcmp.ge $dst, p0 = $src1, $src2",
-	  [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF;
+          [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF;
 
 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$qp),
     "($qp) cmp.eq.unc $dst, p0 = r0, r0">, isA;
 
 def : Pat<(trunc GR:$src),  // truncate i64 to i1
           (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true
-	  
+
 let isTwoAddress=1 in {
   def TPCMPEQR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp),
     "($qp) cmp.eq $dst, p0 = r0, r0">, isA;
@@ -355,7 +355,7 @@ def bOR   : Pat<(or PR:$src1, PR:$src2),
 
 def bAND  : Pat<(and PR:$src1, PR:$src2),
           ( TPCMPNER0R0 (PCMPEQUNCR0R0 PR:$src1),
-	    (TPCMPNER0R0 (CMPEQ r0, r0), PR:$src2) )>;
+            (TPCMPNER0R0 (CMPEQ r0, r0), PR:$src2) )>;
 
 /* one possible routine for XOR on predicates is:
 
@@ -391,12 +391,12 @@ def bAND  : Pat<(and PR:$src1, PR:$src2),
   
 def bXOR  : Pat<(xor PR:$src1, PR:$src2),
           (TPCMPIMM8NE (PCMPEQUNCR0R0 PR:$src2), 1,
-	               (TPCADDS (ADDS r0, 0), 1, PR:$src2),
-                        PR:$src1)>;
+                        (TPCADDS (ADDS r0, 0), 1, PR:$src2),
+                         PR:$src1)>;
 
 def XOR   : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "xor $dst = $src1, $src2",
-	  [(set GR:$dst, (xor GR:$src1, GR:$src2))]>, isA;
+          [(set GR:$dst, (xor GR:$src1, GR:$src2))]>, isA;
 
 def SHLADD: AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1,s64imm:$imm,GR:$src2),
           "shladd $dst = $src1, $imm, $src2",
@@ -404,15 +404,15 @@ def SHLADD: AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1,s64imm:$imm,GR:$
 
 def SHL   : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "shl $dst = $src1, $src2",
-	  [(set GR:$dst, (shl GR:$src1, GR:$src2))]>, isI;
+          [(set GR:$dst, (shl GR:$src1, GR:$src2))]>, isI;
 
 def SHRU  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "shr.u $dst = $src1, $src2",
-	  [(set GR:$dst, (srl GR:$src1, GR:$src2))]>, isI;
+          [(set GR:$dst, (srl GR:$src1, GR:$src2))]>, isI;
 
 def SHRS  : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
           "shr $dst = $src1, $src2",
-	  [(set GR:$dst, (sra GR:$src1, GR:$src2))]>, isI;
+          [(set GR:$dst, (sra GR:$src1, GR:$src2))]>, isI;
 
 def MOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "mov $dst = $src">, isA;
 def FMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index 6e28002..83c5d64 100644
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -419,7 +419,7 @@ def GR : RegisterClass<"IA64", [i64], 64,
         r104, r105, r106, r107, r108, r109, r110, r111,
         r112, r113, r114, r115, r116, r117, r118, r119,
         r120, r121, r122, r123, r124, r125, r126, r127,
-	r0, r1, r2, r5, r12, r13, r22, rp]> // the last 16 are special (look down)
+        r0, r1, r2, r5, r12, r13, r22, rp]> // last 16 are special (look down)
   {
     let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
@@ -428,19 +428,18 @@ def GR : RegisterClass<"IA64", [i64], 64,
   let MethodBodies = [{
     GRClass::iterator
     GRClass::allocation_order_begin(const MachineFunction &MF) const {
-	// hide the 8 out? registers appropriately:
-	return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
+        // hide the 8 out? registers appropriately:
+        return begin()+(8-(MF.getInfo<IA64FunctionInfo>()->outRegsUsed));
       }
 
       GRClass::iterator
       GRClass::allocation_order_end(const MachineFunction &MF) const {
-	int numReservedRegs=8; // the 8 special registers r0,r1,r2,r5,r12,r13 etc
+        int numReservedRegs=8;// the 8 special registers r0,r1,r2,r5,r12,r13 etc
 
-	// we also can't allocate registers for use as locals if they're
-	// already required as 'out' registers
-	numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
-	
-	return end()-numReservedRegs; // hide registers appropriately
+        // we also can't allocate registers for use as locals if they're already
+        // required as 'out' registers
+        numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
+        return end()-numReservedRegs; // hide registers appropriately
       }
   }];
 }
@@ -450,20 +449,20 @@ def GR : RegisterClass<"IA64", [i64], 64,
 
 def FP : RegisterClass<"IA64", [f64], 64, 
        [F6, F7, 
-	F8, F9, F10, F11, F12, F13, F14, F15, 
-	F32, F33, F34, F35, F36, F37, F38, F39, 
-	F40, F41, F42, F43, F44, F45, F46, F47, 
-	F48, F49, F50, F51, F52, F53, F54, F55, 
-	F56, F57, F58, F59, F60, F61, F62, F63, 
-	F64, F65, F66, F67, F68, F69, F70, F71, 
-	F72, F73, F74, F75, F76, F77, F78, F79, 
-	F80, F81, F82, F83, F84, F85, F86, F87, 
-	F88, F89, F90, F91, F92, F93, F94, F95, 
-	F96, F97, F98, F99, F100, F101, F102, F103, 
-	F104, F105, F106, F107, F108, F109, F110, F111, 
-	F112, F113, F114, F115, F116, F117, F118, F119, 
-	F120, F121, F122, F123, F124, F125, F126, F127,
-	F0, F1]> // these last two are hidden
+        F8, F9, F10, F11, F12, F13, F14, F15, 
+        F32, F33, F34, F35, F36, F37, F38, F39, 
+        F40, F41, F42, F43, F44, F45, F46, F47, 
+        F48, F49, F50, F51, F52, F53, F54, F55, 
+        F56, F57, F58, F59, F60, F61, F62, F63, 
+        F64, F65, F66, F67, F68, F69, F70, F71, 
+        F72, F73, F74, F75, F76, F77, F78, F79, 
+        F80, F81, F82, F83, F84, F85, F86, F87, 
+        F88, F89, F90, F91, F92, F93, F94, F95, 
+        F96, F97, F98, F99, F100, F101, F102, F103, 
+        F104, F105, F106, F107, F108, F109, F110, F111, 
+        F112, F113, F114, F115, F116, F117, F118, F119, 
+        F120, F121, F122, F123, F124, F125, F126, F127,
+        F0, F1]> // these last two are hidden
   {
 // the 128s here are to make stf.spill/ldf.fill happy,
 // when storing full (82-bit) FP regs to stack slots
@@ -478,13 +477,13 @@ def FP : RegisterClass<"IA64", [f64], 64,
   let MethodBodies = [{
     FPClass::iterator
     FPClass::allocation_order_begin(const MachineFunction &MF) const {
-	return begin(); // we don't hide any FP regs from the start
-      }
+      return begin(); // we don't hide any FP regs from the start
+    }
 
-      FPClass::iterator
-      FPClass::allocation_order_end(const MachineFunction &MF) const {
-	return end()-2; // we hide regs F0, F1 from the end 
-      }
+    FPClass::iterator
+    FPClass::allocation_order_end(const MachineFunction &MF) const {
+      return end()-2; // we hide regs F0, F1 from the end 
+    }
   }];
 }
 
diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp
index 4ad57c9..dc3242c 100644
--- a/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -110,11 +110,11 @@ FunctionPass *llvm::createMipsCodePrinterPass(std::ostream &o,
 //
 //  Consider the following function prologue:
 //
-//    .frame	$fp,48,$ra
-//    .mask	  0xc0000000,-8
-//	  addiu $sp, $sp, -48
-//	  sw $ra, 40($sp)
-//	  sw $fp, 36($sp)
+//    .frame  $fp,48,$ra
+//    .mask   0xc0000000,-8
+//       addiu $sp, $sp, -48
+//       sw $ra, 40($sp)
+//       sw $fp, 36($sp)
 //
 //    With a 0xc0000000 mask, the assembler knows the register 31 (RA) and 
 //    30 (FP) are saved at prologue. As the save order on prologue is from 
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 212268c..556b014 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -106,13 +106,13 @@ def PPCcall_ELF   : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
 def PPCmtctr      : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 def PPCbctrl_Macho  : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
-	                   [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 def PPCbctrl_ELF  : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
-	                   [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 def retflag       : SDNode<"PPCISD::RET_FLAG", SDTNone,
-	                   [SDNPHasChain, SDNPOptInFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag]>;
 
 def PPCvcmp       : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
 def PPCvcmp_o     : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 71fa887..c9fba9d 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -125,11 +125,11 @@ def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,
 
 def SDT_SPCall    : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
 def call          : SDNode<"SPISD::CALL", SDT_SPCall,
-	                   [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
 
 def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
 def retflag       : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
-	                   [SDNPHasChain, SDNPOptInFlag]>;
+                           [SDNPHasChain, SDNPOptInFlag]>;
 
 //===----------------------------------------------------------------------===//
 // SPARC Flag Conditions