diff options
| author | Dan Gohman <gohman@apple.com> | 2008-02-10 18:45:23 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-02-10 18:45:23 +0000 |
| commit | 6f0d024a534af18d9e60b3ea757376cd8a3a980e (patch) | |
| tree | 24ca65a47eb4948b2fbbc5cfeb1ebfc270bcd45e /lib | |
| parent | 6bbba6691e66178a895e3c50cfc553eaf9ace2d0 (diff) | |
| download | external_llvm-6f0d024a534af18d9e60b3ea757376cd8a3a980e.zip external_llvm-6f0d024a534af18d9e60b3ea757376cd8a3a980e.tar.gz external_llvm-6f0d024a534af18d9e60b3ea757376cd8a3a980e.tar.bz2 | |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
88 files changed, 536 insertions, 521 deletions
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index 16f9b89..dc67593 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -24,7 +24,7 @@ #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/ADT/Statistic.h" @@ -72,7 +72,7 @@ namespace { MachineBasicBlock::iterator BBI1); std::vector<std::pair<unsigned,MachineBasicBlock*> > MergePotentials; - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; RegScavenger *RS; // Branch optzn. bool OptimizeBranches(MachineFunction &MF); diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp index 96f7c19..8cc7f30 100644 --- a/lib/CodeGen/DwarfWriter.cpp +++ b/lib/CodeGen/DwarfWriter.cpp @@ -30,7 +30,7 @@ #include "llvm/Support/Mangler.h" #include "llvm/System/Path.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -782,7 +782,7 @@ protected: const TargetData *TD; /// RI - Register Information. - const MRegisterInfo *RI; + const TargetRegisterInfo *RI; /// M - Current module. /// diff --git a/lib/CodeGen/LiveInterval.cpp b/lib/CodeGen/LiveInterval.cpp index e1b8cf9..22ebf3b 100644 --- a/lib/CodeGen/LiveInterval.cpp +++ b/lib/CodeGen/LiveInterval.cpp @@ -22,7 +22,7 @@ #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Streams.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include <algorithm> #include <ostream> using namespace llvm; @@ -589,9 +589,10 @@ void LiveRange::dump() const { cerr << *this << "\n"; } -void LiveInterval::print(std::ostream &OS, const MRegisterInfo *MRI) const { - if (MRI && MRegisterInfo::isPhysicalRegister(reg)) - OS << MRI->getName(reg); +void LiveInterval::print(std::ostream &OS, + const TargetRegisterInfo *TRI) const { + if (TRI && TargetRegisterInfo::isPhysicalRegister(reg)) + OS << TRI->getName(reg); else OS << "%reg" << reg; diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp index b508ac2..43a092a 100644 --- a/lib/CodeGen/LiveIntervalAnalysis.cpp +++ b/lib/CodeGen/LiveIntervalAnalysis.cpp @@ -25,7 +25,7 @@ #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/CommandLine.h" @@ -100,10 +100,10 @@ namespace llvm { bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); lv_ = &getAnalysis<LiveVariables>(); - allocatableRegs_ = mri_->getAllocatableSet(fn); + allocatableRegs_ = tri_->getAllocatableSet(fn); // Number MachineInstrs and MachineBasicBlocks. // Initialize MBB indexes to a sentinal. @@ -134,7 +134,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { DOUT << "********** INTERVALS **********\n"; for (iterator I = begin(), E = end(); I != E; ++I) { - I->second.print(DOUT, mri_); + I->second.print(DOUT, tri_); DOUT << "\n"; } @@ -147,7 +147,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) { void LiveIntervals::print(std::ostream &O, const Module* ) const { O << "********** INTERVALS **********\n"; for (const_iterator I = begin(), E = end(); I != E; ++I) { - I->second.print(DOUT, mri_); + I->second.print(DOUT, tri_); DOUT << "\n"; } @@ -188,12 +188,12 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, unsigned PhysReg = mop.getReg(); if (PhysReg == 0 || PhysReg == li.reg) continue; - if (MRegisterInfo::isVirtualRegister(PhysReg)) { + if (TargetRegisterInfo::isVirtualRegister(PhysReg)) { if (!vrm.hasPhys(PhysReg)) continue; PhysReg = vrm.getPhys(PhysReg); } - if (PhysReg && mri_->regsOverlap(PhysReg, reg)) + if (PhysReg && tri_->regsOverlap(PhysReg, reg)) return true; } } @@ -203,8 +203,8 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li, } void LiveIntervals::printRegName(unsigned reg) const { - if (MRegisterInfo::isPhysicalRegister(reg)) - cerr << mri_->getName(reg); + if (TargetRegisterInfo::isPhysicalRegister(reg)) + cerr << tri_->getName(reg); else cerr << "%reg" << reg; } @@ -347,7 +347,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, interval.addRange(LiveRange(RedefIndex, RedefIndex+1, OldValNo)); DOUT << " RESULT: "; - interval.print(DOUT, mri_); + interval.print(DOUT, tri_); } else { // Otherwise, this must be because of phi elimination. If this is the @@ -363,11 +363,11 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, unsigned Start = getMBBStartIdx(Killer->getParent()); unsigned End = getUseIndex(getInstructionIndex(Killer))+1; DOUT << " Removing [" << Start << "," << End << "] from: "; - interval.print(DOUT, mri_); DOUT << "\n"; + interval.print(DOUT, tri_); DOUT << "\n"; interval.removeRange(Start, End); interval.addKill(VNI, Start); VNI->hasPHIKill = true; - DOUT << " RESULT: "; interval.print(DOUT, mri_); + DOUT << " RESULT: "; interval.print(DOUT, tri_); // Replace the interval with one of a NEW value number. Note that this // value number isn't actually defined by an instruction, weird huh? :) @@ -375,7 +375,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb, DOUT << " replace range with " << LR; interval.addRange(LR); interval.addKill(LR.valno, End); - DOUT << " RESULT: "; interval.print(DOUT, mri_); + DOUT << " RESULT: "; interval.print(DOUT, tri_); } // In the case of PHI elimination, each variable definition is only @@ -470,7 +470,7 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, MachineBasicBlock::iterator MI, unsigned MIIdx, unsigned reg) { - if (MRegisterInfo::isVirtualRegister(reg)) + if (TargetRegisterInfo::isVirtualRegister(reg)) handleVirtualRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg)); else if (allocatableRegs_[reg]) { unsigned SrcReg, DstReg; @@ -480,7 +480,7 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB, SrcReg = 0; handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(reg), SrcReg); // Def of a register also defines its sub-registers. - for (const unsigned* AS = mri_->getSubRegisters(reg); *AS; ++AS) + for (const unsigned* AS = tri_->getSubRegisters(reg); *AS; ++AS) // Avoid processing some defs more than once. if (!MI->findRegisterDefOperand(*AS)) handlePhysicalRegisterDef(MBB, MI, MIIdx, getOrCreateInterval(*AS), 0); @@ -557,7 +557,7 @@ void LiveIntervals::computeIntervals() { LE = MBB->livein_end(); LI != LE; ++LI) { handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*LI)); // Multiple live-ins can alias the same register. - for (const unsigned* AS = mri_->getSubRegisters(*LI); *AS; ++AS) + for (const unsigned* AS = tri_->getSubRegisters(*LI); *AS; ++AS) if (!hasInterval(*AS)) handleLiveInRegister(MBB, MIIndex, getOrCreateInterval(*AS), true); @@ -597,7 +597,7 @@ bool LiveIntervals::findLiveInMBBs(const LiveRange &LR, LiveInterval LiveIntervals::createInterval(unsigned reg) { - float Weight = MRegisterInfo::isPhysicalRegister(reg) ? + float Weight = TargetRegisterInfo::isPhysicalRegister(reg) ? HUGE_VALF : 0.0F; return LiveInterval(reg, Weight); } @@ -717,7 +717,7 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI, if (lv_) lv_->instructionChanged(MI, fmi); else - fmi->copyKillDeadInfo(MI, mri_); + fmi->copyKillDeadInfo(MI, tri_); MachineBasicBlock &MBB = *MI->getParent(); if (isSS && !mf_->getFrameInfo()->isImmutableObjectIndex(Slot)) vrm.virtFolded(Reg, MI, fmi, (VirtRegMap::ModRef)MRInfo); @@ -789,7 +789,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit, continue; unsigned Reg = mop.getReg(); unsigned RegI = Reg; - if (Reg == 0 || MRegisterInfo::isPhysicalRegister(Reg)) + if (Reg == 0 || TargetRegisterInfo::isPhysicalRegister(Reg)) continue; if (Reg != li.reg) continue; @@ -840,7 +840,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit, if (!MOj.isRegister()) continue; unsigned RegJ = MOj.getReg(); - if (RegJ == 0 || MRegisterInfo::isPhysicalRegister(RegJ)) + if (RegJ == 0 || TargetRegisterInfo::isPhysicalRegister(RegJ)) continue; if (RegJ == RegI) { Ops.push_back(j); @@ -939,7 +939,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit, } DOUT << "\t\t\t\tAdded new interval: "; - nI.print(DOUT, mri_); + nI.print(DOUT, tri_); DOUT << '\n'; } return CanFold; @@ -1181,7 +1181,7 @@ addIntervalsForSpills(const LiveInterval &li, "attempt to spill already spilled interval!"); DOUT << "\t\t\t\tadding intervals for spills for interval: "; - li.print(DOUT, mri_); + li.print(DOUT, tri_); DOUT << '\n'; // Each bit specify whether it a spill is required in the MBB. diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 70c191d..34ad238 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -29,7 +29,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DepthFirstIterator.h" @@ -60,9 +60,9 @@ void LiveVariables::VarInfo::dump() const { } LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { - assert(MRegisterInfo::isVirtualRegister(RegIdx) && + assert(TargetRegisterInfo::isVirtualRegister(RegIdx) && "getVarInfo: not a virtual register!"); - RegIdx -= MRegisterInfo::FirstVirtualRegister; + RegIdx -= TargetRegisterInfo::FirstVirtualRegister; if (RegIdx >= VirtRegInfo.size()) { if (RegIdx >= 2*VirtRegInfo.size()) VirtRegInfo.resize(RegIdx*2); @@ -80,8 +80,8 @@ bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isKill()) { if ((MO.getReg() == Reg) || - (MRegisterInfo::isPhysicalRegister(MO.getReg()) && - MRegisterInfo::isPhysicalRegister(Reg) && + (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + TargetRegisterInfo::isPhysicalRegister(Reg) && RegInfo->isSubRegister(MO.getReg(), Reg))) return true; } @@ -94,8 +94,8 @@ bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDead()) { if ((MO.getReg() == Reg) || - (MRegisterInfo::isPhysicalRegister(MO.getReg()) && - MRegisterInfo::isPhysicalRegister(Reg) && + (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + TargetRegisterInfo::isPhysicalRegister(Reg) && RegInfo->isSubRegister(MO.getReg(), Reg))) return true; } @@ -399,7 +399,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { // Mark live-in registers as live-in. for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(), EE = MBB->livein_end(); II != EE; ++II) { - assert(MRegisterInfo::isPhysicalRegister(*II) && + assert(TargetRegisterInfo::isPhysicalRegister(*II) && "Cannot have a live-in virtual register!"); HandlePhysRegDef(*II, 0); } @@ -421,9 +421,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isUse() && MO.getReg()) { - if (MRegisterInfo::isVirtualRegister(MO.getReg())){ + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())){ HandleVirtRegUse(MO.getReg(), MBB, MI); - } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && + } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && !ReservedRegisters[MO.getReg()]) { HandlePhysRegUse(MO.getReg(), MI); } @@ -434,12 +434,12 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg()) { - if (MRegisterInfo::isVirtualRegister(MO.getReg())) { + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { VarInfo &VRInfo = getVarInfo(MO.getReg()); if (VRInfo.AliveBlocks.none()) // If vr is not alive in any block, then defaults to dead. VRInfo.Kills.push_back(MI); - } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && + } else if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && !ReservedRegisters[MO.getReg()]) { HandlePhysRegDef(MO.getReg(), MI); } @@ -469,7 +469,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { for (MachineRegisterInfo::liveout_iterator I = MF->getRegInfo().liveout_begin(), E = MF->getRegInfo().liveout_end(); I != E; ++I) { - assert(MRegisterInfo::isPhysicalRegister(*I) && + assert(TargetRegisterInfo::isPhysicalRegister(*I) && "Cannot have a live-in virtual register!"); HandlePhysRegUse(*I, Ret); // Add live-out registers as implicit uses. @@ -498,13 +498,13 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) { if (VirtRegInfo[i].Kills[j] == MRI.getVRegDef(i + - MRegisterInfo::FirstVirtualRegister)) + TargetRegisterInfo::FirstVirtualRegister)) VirtRegInfo[i].Kills[j]->addRegisterDead(i + - MRegisterInfo::FirstVirtualRegister, + TargetRegisterInfo::FirstVirtualRegister, RegInfo); else VirtRegInfo[i].Kills[j]->addRegisterKilled(i + - MRegisterInfo::FirstVirtualRegister, + TargetRegisterInfo::FirstVirtualRegister, RegInfo); } @@ -536,7 +536,7 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI, for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = OldMI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); VarInfo &VI = getVarInfo(Reg); if (MO.isDef()) { @@ -564,7 +564,7 @@ void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { if (MO.isRegister() && MO.isKill()) { MO.setIsKill(false); unsigned Reg = MO.getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) { bool removed = getVarInfo(Reg).removeKill(MI); assert(removed && "kill not in register's VarInfo?"); } @@ -580,7 +580,7 @@ void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { if (MO.isRegister() && MO.isDead()) { MO.setIsDead(false); unsigned Reg = MO.getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) { bool removed = getVarInfo(Reg).removeKill(MI); assert(removed && "kill not in register's VarInfo?"); } diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 4172b12..232dc06 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" @@ -46,13 +46,13 @@ FunctionPass *llvm::createLowerSubregsPass() { // Returns the Register Class of a physical register. static const TargetRegisterClass *getPhysicalRegisterRegClass( - const MRegisterInfo &MRI, + const TargetRegisterInfo &TRI, unsigned reg) { - assert(MRegisterInfo::isPhysicalRegister(reg) && + assert(TargetRegisterInfo::isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the register class of the right type that contains this physreg. - for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(), - E = MRI.regclass_end(); I != E; ++I) + for (TargetRegisterInfo::regclass_iterator I = TRI.regclass_begin(), + E = TRI.regclass_end(); I != E; ++I) if ((*I)->contains(reg)) return *I; assert(false && "Couldn't find the register class"); @@ -62,7 +62,7 @@ static const TargetRegisterClass *getPhysicalRegisterRegClass( bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); - const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() && @@ -72,21 +72,21 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { unsigned SuperReg = MI->getOperand(1).getReg(); unsigned SubIdx = MI->getOperand(2).getImm(); - assert(MRegisterInfo::isPhysicalRegister(SuperReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) && "Extract supperg source must be a physical register"); - unsigned SrcReg = MRI.getSubReg(SuperReg, SubIdx); + unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx); unsigned DstReg = MI->getOperand(0).getReg(); DOUT << "subreg: CONVERTING: " << *MI; if (SrcReg != DstReg) { const TargetRegisterClass *TRC = 0; - if (MRegisterInfo::isPhysicalRegister(DstReg)) { - TRC = getPhysicalRegisterRegClass(MRI, DstReg); + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { + TRC = getPhysicalRegisterRegClass(TRI, DstReg); } else { TRC = MF.getRegInfo().getRegClass(DstReg); } - assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && + assert(TRC == getPhysicalRegisterRegClass(TRI, SrcReg) && "Extract subreg and Dst must be of same register class"); TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); @@ -103,7 +103,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { MachineBasicBlock *MBB = MI->getParent(); MachineFunction &MF = *MBB->getParent(); - const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); unsigned DstReg = 0; unsigned SrcReg = 0; @@ -133,13 +133,13 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(0 && "Malformed extract_subreg"); assert(SubIdx != 0 && "Invalid index for extract_subreg"); - unsigned DstSubReg = MRI.getSubReg(DstReg, SubIdx); + unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); - assert(MRegisterInfo::isPhysicalRegister(SrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && "Insert superreg source must be in a physical register"); - assert(MRegisterInfo::isPhysicalRegister(DstReg) && + assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && "Insert destination must be in a physical register"); - assert(MRegisterInfo::isPhysicalRegister(InsReg) && + assert(TargetRegisterInfo::isPhysicalRegister(InsReg) && "Inserted value must be in a physical register"); DOUT << "subreg: CONVERTING: " << *MI; @@ -148,14 +148,14 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { // of the destination, we copy the subreg into the source // However, this is only safe if the insert instruction is the kill // of the source register - bool revCopyOrder = MRI.isSubRegister(DstReg, InsReg); + bool revCopyOrder = TRI.isSubRegister(DstReg, InsReg); if (revCopyOrder && InsReg != DstSubReg) { if (MI->getOperand(1).isKill()) { - DstSubReg = MRI.getSubReg(SrcReg, SubIdx); + DstSubReg = TRI.getSubReg(SrcReg, SubIdx); // Insert sub-register copy const TargetRegisterClass *TRC1 = 0; - if (MRegisterInfo::isPhysicalRegister(InsReg)) { - TRC1 = getPhysicalRegisterRegClass(MRI, InsReg); + if (TargetRegisterInfo::isPhysicalRegister(InsReg)) { + TRC1 = getPhysicalRegisterRegClass(TRI, InsReg); } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } @@ -178,12 +178,12 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { if (SrcReg != DstReg) { // Insert super-register copy const TargetRegisterClass *TRC0 = 0; - if (MRegisterInfo::isPhysicalRegister(DstReg)) { - TRC0 = getPhysicalRegisterRegClass(MRI, DstReg); + if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { + TRC0 = getPhysicalRegisterRegClass(TRI, DstReg); } else { TRC0 = MF.getRegInfo().getRegClass(DstReg); } - assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && + assert(TRC0 == getPhysicalRegisterRegClass(TRI, SrcReg) && "Insert superreg and Dst must be of same register class"); TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); @@ -203,8 +203,8 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { if (!revCopyOrder && InsReg != DstSubReg) { // Insert sub-register copy const TargetRegisterClass *TRC1 = 0; - if (MRegisterInfo::isPhysicalRegister(InsReg)) { - TRC1 = getPhysicalRegisterRegClass(MRI, InsReg); + if (TargetRegisterInfo::isPhysicalRegister(InsReg)) { + TRC1 = getPhysicalRegisterRegClass(TRI, InsReg); } else { TRC1 = MF.getRegInfo().getRegClass(InsReg); } diff --git a/lib/CodeGen/MachineBasicBlock.cpp b/lib/CodeGen/MachineBasicBlock.cpp index aba3f87..dc6a618 100644 --- a/lib/CodeGen/MachineBasicBlock.cpp +++ b/lib/CodeGen/MachineBasicBlock.cpp @@ -14,7 +14,7 @@ #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/BasicBlock.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetInstrDesc.h" #include "llvm/Target/TargetMachine.h" @@ -143,10 +143,10 @@ void MachineBasicBlock::dump() const { } static inline void OutputReg(std::ostream &os, unsigned RegNo, - const MRegisterInfo *MRI = 0) { - if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { - if (MRI) - os << " %" << MRI->get(RegNo).Name; + const TargetRegisterInfo *TRI = 0) { + if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) { + if (TRI) + os << " %" << TRI->get(RegNo).Name; else os << " %mreg(" << RegNo << ")"; } else @@ -169,11 +169,11 @@ void MachineBasicBlock::print(std::ostream &OS) const { if (isLandingPad()) OS << ", EH LANDING PAD"; OS << ":\n"; - const MRegisterInfo *MRI = MF->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); if (!livein_empty()) { OS << "Live Ins:"; for (const_livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I) - OutputReg(OS, *I, MRI); + OutputReg(OS, *I, TRI); OS << "\n"; } // Print the preds of this block according to the CFG. diff --git a/lib/CodeGen/MachineFunction.cpp b/lib/CodeGen/MachineFunction.cpp index 8c9bbf3..3089617 100644 --- a/lib/CodeGen/MachineFunction.cpp +++ b/lib/CodeGen/MachineFunction.cpp @@ -207,14 +207,14 @@ void MachineFunction::print(std::ostream &OS) const { // Print Constant Pool getConstantPool()->print(OS); - const MRegisterInfo *MRI = getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = getTarget().getRegisterInfo(); if (!RegInfo->livein_empty()) { OS << "Live Ins:"; for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) { - if (MRI) - OS << " " << MRI->getName(I->first); + if (TRI) + OS << " " << TRI->getName(I->first); else OS << " Reg #" << I->first; @@ -227,8 +227,8 @@ void MachineFunction::print(std::ostream &OS) const { OS << "Live Outs:"; for (MachineRegisterInfo::liveout_iterator I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I) - if (MRI) - OS << " " << MRI->getName(*I); + if (TRI) + OS << " " << TRI->getName(*I); else OS << " Reg #" << *I; OS << "\n"; diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 5744ba8..d576caf 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -20,7 +20,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrDesc.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/LeakDetector.h" #include "llvm/Support/Streams.h" #include <ostream> @@ -159,7 +159,7 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const { switch (getType()) { case MachineOperand::MO_Register: - if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) { + if (getReg() == 0 || TargetRegisterInfo::isVirtualRegister(getReg())) { OS << "%reg" << getReg(); } else { // If the instruction is embedded into a basic block, we can find the @@ -666,7 +666,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { } bool MachineInstr::addRegisterKilled(unsigned IncomingReg, - const MRegisterInfo *RegInfo, + const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { bool Found = false; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { @@ -679,8 +679,8 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, MO.setIsKill(); Found = true; break; - } else if (MRegisterInfo::isPhysicalRegister(Reg) && - MRegisterInfo::isPhysicalRegister(IncomingReg) && + } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isKill()) // A super-register kill already exists. @@ -699,7 +699,7 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, } bool MachineInstr::addRegisterDead(unsigned IncomingReg, - const MRegisterInfo *RegInfo, + const TargetRegisterInfo *RegInfo, bool AddIfNotFound) { bool Found = false; for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { @@ -712,8 +712,8 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg, MO.setIsDead(); Found = true; break; - } else if (MRegisterInfo::isPhysicalRegister(Reg) && - MRegisterInfo::isPhysicalRegister(IncomingReg) && + } else if (TargetRegisterInfo::isPhysicalRegister(Reg) && + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && RegInfo->isSuperRegister(IncomingReg, Reg) && MO.isDead()) // There exists a super-register that's marked dead. @@ -734,13 +734,13 @@ bool MachineInstr::addRegisterDead(unsigned IncomingReg, /// copyKillDeadInfo - copies killed/dead information from one instr to another void MachineInstr::copyKillDeadInfo(MachineInstr *OldMI, - const MRegisterInfo *RegInfo) { + const TargetRegisterInfo *RegInfo) { // If the instruction defines any virtual registers, update the VarInfo, // kill and dead information for the instruction. for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = OldMI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (MO.isDef()) { if (MO.isDead()) { diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp index 92256eb..89ab93d 100644 --- a/lib/CodeGen/MachineLICM.cpp +++ b/lib/CodeGen/MachineLICM.cpp @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" @@ -248,19 +248,19 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { if (I.getDesc().getImplicitUses()) { DOUT << " * Instruction has implicit uses:\n"; - const MRegisterInfo *MRI = TM->getRegisterInfo(); + const TargetRegisterInfo *TRI = TM->getRegisterInfo(); for (const unsigned *ImpUses = I.getDesc().getImplicitUses(); *ImpUses; ++ImpUses) - DOUT << " -> " << MRI->getName(*ImpUses) << "\n"; + DOUT << " -> " << TRI->getName(*ImpUses) << "\n"; } if (I.getDesc().getImplicitDefs()) { DOUT << " * Instruction has implicit defines:\n"; - const MRegisterInfo *MRI = TM->getRegisterInfo(); + const TargetRegisterInfo *TRI = TM->getRegisterInfo(); for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs(); *ImpDefs; ++ImpDefs) - DOUT << " -> " << MRI->getName(*ImpDefs) << "\n"; + DOUT << " -> " << TRI->getName(*ImpDefs) << "\n"; } //if (TII->hasUnmodelledSideEffects(&I)) @@ -277,7 +277,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) { unsigned Reg = MO.getReg(); // Don't hoist instructions that access physical registers. - if (!MRegisterInfo::isVirtualRegister(Reg)) + if (!TargetRegisterInfo::isVirtualRegister(Reg)) return false; assert(RegInfo->getVRegDef(Reg)&&"Machine instr not mapped for this vreg?"); diff --git a/lib/CodeGen/MachineRegisterInfo.cpp b/lib/CodeGen/MachineRegisterInfo.cpp index dbb01c3..62c9506 100644 --- a/lib/CodeGen/MachineRegisterInfo.cpp +++ b/lib/CodeGen/MachineRegisterInfo.cpp @@ -14,13 +14,13 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" using namespace llvm; -MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) { +MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { VRegInfo.reserve(256); - UsedPhysRegs.resize(MRI.getNumRegs()); + UsedPhysRegs.resize(TRI.getNumRegs()); // Create the physreg use/def lists. - PhysRegUseDefLists = new MachineOperand*[MRI.getNumRegs()]; - memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*MRI.getNumRegs()); + PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; + memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); } MachineRegisterInfo::~MachineRegisterInfo() { @@ -64,7 +64,7 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) { /// register or null if none is found. This assumes that the code is in SSA /// form, so there should only be one definition. MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const { - assert(Reg-MRegisterInfo::FirstVirtualRegister < VRegInfo.size() && + assert(Reg-TargetRegisterInfo::FirstVirtualRegister < VRegInfo.size() && "Invalid vreg!"); for (reg_iterator I = reg_begin(Reg), E = reg_end(); I != E; ++I) { // Since we are in SSA form, we can stop at the first definition. diff --git a/lib/CodeGen/MachineSink.cpp b/lib/CodeGen/MachineSink.cpp index 29b0b3f..db2fab0 100644 --- a/lib/CodeGen/MachineSink.cpp +++ b/lib/CodeGen/MachineSink.cpp @@ -15,7 +15,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineDominators.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/SmallVector.h" @@ -61,7 +61,8 @@ FunctionPass *llvm::createMachineSinkingPass() { return new MachineSinking(); } /// occur in blocks dominated by the specified block. bool MachineSinking::AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Only makes sense for vregs"); + assert(TargetRegisterInfo::isVirtualRegister(Reg) && + "Only makes sense for vregs"); for (MachineRegisterInfo::reg_iterator I = RegInfo->reg_begin(Reg), E = RegInfo->reg_end(); I != E; ++I) { if (I.getOperand().isDef()) continue; // ignore def. @@ -179,7 +180,7 @@ bool MachineSinking::SinkInstruction(MachineInstr *MI, bool &SawStore) { unsigned Reg = MO.getReg(); if (Reg == 0) continue; - if (MRegisterInfo::isPhysicalRegister(Reg)) { + if (TargetRegisterInfo::isPhysicalRegister(Reg)) { // If this is a physical register use, we can't move it. If it is a def, // we can move it, but only if the def is dead. if (MO.isUse() || !MO.isDead()) diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp index 45f1c5d..845b1c1 100644 --- a/lib/CodeGen/PHIElimination.cpp +++ b/lib/CodeGen/PHIElimination.cpp @@ -181,7 +181,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB, std::set<MachineBasicBlock*> MBBsInsertedInto; for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) { unsigned SrcReg = MPhi->getOperand(i-1).getReg(); - assert(MRegisterInfo::isVirtualRegister(SrcReg) && + assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && "Machine PHI Operands must all be virtual registers!"); // Get the MachineBasicBlock equivalent of the BasicBlock that is the diff --git a/lib/CodeGen/PhysRegTracker.h b/lib/CodeGen/PhysRegTracker.h index b300d4d..1f10c4b 100644 --- a/lib/CodeGen/PhysRegTracker.h +++ b/lib/CodeGen/PhysRegTracker.h @@ -17,52 +17,52 @@ #ifndef LLVM_CODEGEN_PHYSREGTRACKER_H #define LLVM_CODEGEN_PHYSREGTRACKER_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { class PhysRegTracker { - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; std::vector<unsigned> regUse_; public: - explicit PhysRegTracker(const MRegisterInfo& mri) - : mri_(&mri), - regUse_(mri_->getNumRegs(), 0) { + explicit PhysRegTracker(const TargetRegisterInfo& tri) + : tri_(&tri), + regUse_(tri_->getNumRegs(), 0) { } PhysRegTracker(const PhysRegTracker& rhs) - : mri_(rhs.mri_), + : tri_(rhs.tri_), regUse_(rhs.regUse_) { } const PhysRegTracker& operator=(const PhysRegTracker& rhs) { - mri_ = rhs.mri_; + tri_ = rhs.tri_; regUse_ = rhs.regUse_; return *this; } void addRegUse(unsigned physReg) { - assert(MRegisterInfo::isPhysicalRegister(physReg) && + assert(TargetRegisterInfo::isPhysicalRegister(physReg) && "should be physical register!"); ++regUse_[physReg]; - for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) + for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) ++regUse_[*as]; } void delRegUse(unsigned physReg) { - assert(MRegisterInfo::isPhysicalRegister(physReg) && + assert(TargetRegisterInfo::isPhysicalRegister(physReg) && "should be physical register!"); assert(regUse_[physReg] != 0); --regUse_[physReg]; - for (const unsigned* as = mri_->getAliasSet(physReg); *as; ++as) { + for (const unsigned* as = tri_->getAliasSet(physReg); *as; ++as) { assert(regUse_[*as] != 0); --regUse_[*as]; } } bool isRegAvail(unsigned physReg) const { - assert(MRegisterInfo::isPhysicalRegister(physReg) && + assert(TargetRegisterInfo::isPhysicalRegister(physReg) && "should be physical register!"); return regUse_[physReg] == 0; } diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index f30d7d4..f237cbe 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -24,7 +24,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/Compiler.h" @@ -45,8 +45,8 @@ namespace { /// frame indexes with appropriate references. /// bool runOnMachineFunction(MachineFunction &Fn) { - const MRegisterInfo *MRI = Fn.getTarget().getRegisterInfo(); - RS = MRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; + const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); + RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; // Get MachineModuleInfo so that we can track the construction of the // frame. @@ -55,7 +55,7 @@ namespace { // Allow the target machine to make some adjustments to the function // e.g. UsedPhysRegs before calculateCalleeSavedRegisters. - MRI->processFunctionBeforeCalleeSavedScan(Fn, RS); + TRI->processFunctionBeforeCalleeSavedScan(Fn, RS); // Scan the function for modified callee saved registers and insert spill // code for any callee saved registers that are modified. Also calculate @@ -118,7 +118,7 @@ FunctionPass *llvm::createPrologEpilogCodeInserter() { return new PEI(); } /// instructions. /// void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) { - const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo(); // Get the callee saved register list... @@ -377,7 +377,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { // Make sure the special register scavenging spill slot is closest to the // frame pointer if a frame pointer is required. - const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); + const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); if (RS && RegInfo->hasFP(Fn)) { int SFI = RS->getScavengingFrameIndex(); if (SFI >= 0) { @@ -500,12 +500,12 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) { const TargetMachine &TM = Fn.getTarget(); assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); - const MRegisterInfo &MRI = *TM.getRegisterInfo(); + const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); const TargetFrameInfo *TFI = TM.getFrameInfo(); bool StackGrowsDown = TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; - int FrameSetupOpcode = MRI.getCallFrameSetupOpcode(); - int FrameDestroyOpcode = MRI.getCallFrameDestroyOpcode(); + int FrameSetupOpcode = TRI.getCallFrameSetupOpcode(); + int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode(); for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { int SPAdj = 0; // SP offset due to call frame setup / destroy. @@ -522,7 +522,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) { Size = -Size; SPAdj += Size; MachineBasicBlock::iterator PrevI = prior(I); - MRI.eliminateCallFramePseudoInstr(Fn, *BB, I); + TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); // Visit the instructions created by eliminateCallFramePseudoInstr(). I = next(PrevI); MI = NULL; @@ -535,7 +535,7 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) { if (MI->getOperand(i).isFrameIndex()) { // If this instruction has a FrameIndex operand, we need to use that // target machine register info object to eliminate it. - MRI.eliminateFrameIndex(MI, SPAdj, RS); + TRI.eliminateFrameIndex(MI, SPAdj, RS); // Revisit the instruction in full. Some instructions (e.g. inline // asm instructions) can have multiple frame indices. diff --git a/lib/CodeGen/RegAllocBigBlock.cpp b/lib/CodeGen/RegAllocBigBlock.cpp index e6dc744..f2c45ec 100644 --- a/lib/CodeGen/RegAllocBigBlock.cpp +++ b/lib/CodeGen/RegAllocBigBlock.cpp @@ -95,7 +95,7 @@ namespace { /// RegInfo - For dealing with machine register info (aliases, folds /// etc) - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; typedef SmallVector<unsigned, 2> VRegTimes; @@ -152,8 +152,8 @@ namespace { /// markVirtRegModified - Lets us flip bits in the VirtRegModified bitset /// void markVirtRegModified(unsigned Reg, bool Val = true) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - Reg -= MRegisterInfo::FirstVirtualRegister; + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + Reg -= TargetRegisterInfo::FirstVirtualRegister; if (VirtRegModified.size() <= Reg) VirtRegModified.resize(Reg+1); VirtRegModified[Reg] = Val; @@ -162,10 +162,10 @@ namespace { /// isVirtRegModified - Lets us query the VirtRegModified bitset /// bool isVirtRegModified(unsigned Reg) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size() && "Illegal virtual register!"); - return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; + return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister]; } public: @@ -562,7 +562,7 @@ void RABigBlock::FillVRegReadTable(MachineBasicBlock &MBB) { MachineOperand& MO = MI->getOperand(i); // look for vreg reads.. if (MO.isRegister() && !MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { // ..and add them to the read table. VRegTimes* &Times = VRegReadTable[MO.getReg()]; if(!VRegReadTable[MO.getReg()]) { @@ -675,7 +675,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && - MRegisterInfo::isVirtualRegister(MO.getReg())) + TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -686,7 +686,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = Kills.size(); i != e; ++i) { unsigned VirtReg = Kills[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { // If the virtual register was never materialized into a register, it // might not be in the map, but it won't hurt to zero it out anyway. unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); @@ -721,7 +721,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && - MRegisterInfo::isPhysicalRegister(MO.getReg())) { + TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. // These are extra physical register defs when a sub-register @@ -777,7 +777,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; @@ -796,7 +796,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { unsigned VirtReg = DeadDefs[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; assert(PhysReg != 0); @@ -865,7 +865,7 @@ bool RABigBlock::runOnMachineFunction(MachineFunction &Fn) { Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg()); StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg()); VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() - - MRegisterInfo::FirstVirtualRegister + 1, 0); + TargetRegisterInfo::FirstVirtualRegister + 1, 0); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index 6f850eb..c70ff95 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -23,7 +23,7 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/ADT/EquivalenceClasses.h" @@ -62,7 +62,7 @@ namespace { MachineFunction* mf_; const TargetMachine* tm_; - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; MachineRegisterInfo *reginfo_; BitVector allocatableRegs_; @@ -161,10 +161,10 @@ namespace { for (; i != e; ++i) { DOUT << "\t" << *i->first << " -> "; unsigned reg = i->first->reg; - if (MRegisterInfo::isVirtualRegister(reg)) { + if (TargetRegisterInfo::isVirtualRegister(reg)) { reg = vrm_->getPhys(reg); } - DOUT << mri_->getName(reg) << '\n'; + DOUT << tri_->getName(reg) << '\n'; } } }; @@ -172,17 +172,17 @@ namespace { } void RALinScan::ComputeRelatedRegClasses() { - const MRegisterInfo &MRI = *mri_; + const TargetRegisterInfo &TRI = *tri_; // First pass, add all reg classes to the union, and determine at least one // reg class that each register is in. bool HasAliases = false; - for (MRegisterInfo::regclass_iterator RCI = MRI.regclass_begin(), - E = MRI.regclass_end(); RCI != E; ++RCI) { + for (TargetRegisterInfo::regclass_iterator RCI = TRI.regclass_begin(), + E = TRI.regclass_end(); RCI != E; ++RCI) { RelatedRegClasses.insert(*RCI); for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end(); I != E; ++I) { - HasAliases = HasAliases || *MRI.getAliasSet(*I) != 0; + HasAliases = HasAliases || *TRI.getAliasSet(*I) != 0; const TargetRegisterClass *&PRC = OneClassForEachPhysReg[*I]; if (PRC) { @@ -202,7 +202,7 @@ void RALinScan::ComputeRelatedRegClasses() { for (std::map<unsigned, const TargetRegisterClass*>::iterator I = OneClassForEachPhysReg.begin(), E = OneClassForEachPhysReg.end(); I != E; ++I) - for (const unsigned *AS = MRI.getAliasSet(I->first); *AS; ++AS) + for (const unsigned *AS = TRI.getAliasSet(I->first); *AS; ++AS) RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]); } @@ -224,7 +224,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { unsigned SrcReg, DstReg; if (!CopyMI || !tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) return Reg; - if (MRegisterInfo::isVirtualRegister(SrcReg)) + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) if (!vrm_->isAssignedReg(SrcReg)) return Reg; else @@ -238,7 +238,7 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { // Try to coalesce. if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) { - DOUT << "Coalescing: " << cur << " -> " << mri_->getName(SrcReg) << '\n'; + DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n'; vrm_->clearVirt(cur.reg); vrm_->assignVirt2Phys(cur.reg, SrcReg); ++NumCoalesce; @@ -251,10 +251,10 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { bool RALinScan::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); reginfo_ = &mf_->getRegInfo(); - allocatableRegs_ = mri_->getAllocatableSet(fn); + allocatableRegs_ = tri_->getAllocatableSet(fn); li_ = &getAnalysis<LiveIntervals>(); loopInfo = &getAnalysis<MachineLoopInfo>(); @@ -267,7 +267,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) { if (RelatedRegClasses.empty()) ComputeRelatedRegClasses(); - if (!prt_.get()) prt_.reset(new PhysRegTracker(*mri_)); + if (!prt_.get()) prt_.reset(new PhysRegTracker(*tri_)); vrm_.reset(new VirtRegMap(*mf_)); if (!spiller_.get()) spiller_.reset(createSpiller()); @@ -297,7 +297,7 @@ void RALinScan::initIntervalSets() "interval sets should be empty on initialization"); for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { - if (MRegisterInfo::isPhysicalRegister(i->second.reg)) { + if (TargetRegisterInfo::isPhysicalRegister(i->second.reg)) { reginfo_->setPhysRegUsed(i->second.reg); fixed_.push_back(std::make_pair(&i->second, i->second.begin())); } else @@ -323,7 +323,7 @@ void RALinScan::linearScan() processActiveIntervals(cur->beginNumber()); processInactiveIntervals(cur->beginNumber()); - assert(MRegisterInfo::isVirtualRegister(cur->reg) && + assert(TargetRegisterInfo::isVirtualRegister(cur->reg) && "Can only allocate virtual registers!"); // Allocating a virtual register. try to find a free @@ -340,7 +340,7 @@ void RALinScan::linearScan() IntervalPtr &IP = active_.back(); unsigned reg = IP.first->reg; DOUT << "\tinterval " << *IP.first << " expired\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -359,7 +359,7 @@ void RALinScan::linearScan() for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) { LiveInterval &cur = i->second; unsigned Reg = 0; - bool isPhys = MRegisterInfo::isPhysicalRegister(cur.reg); + bool isPhys = TargetRegisterInfo::isPhysicalRegister(cur.reg); if (isPhys) Reg = i->second.reg; else if (vrm_->isAssignedReg(cur.reg)) @@ -399,7 +399,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint) if (IntervalPos == Interval->end()) { // Remove expired intervals. DOUT << "\t\tinterval " << *Interval << " expired\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -412,7 +412,7 @@ void RALinScan::processActiveIntervals(unsigned CurPoint) } else if (IntervalPos->start > CurPoint) { // Move inactive intervals to inactive list. DOUT << "\t\tinterval " << *Interval << " inactive\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->delRegUse(reg); @@ -453,7 +453,7 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint) } else if (IntervalPos->start <= CurPoint) { // move re-activated intervals in active list DOUT << "\t\tinterval " << *Interval << " active\n"; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); prt_->addRegUse(reg); @@ -475,9 +475,9 @@ void RALinScan::processInactiveIntervals(unsigned CurPoint) /// register and its weight. static void updateSpillWeights(std::vector<float> &Weights, unsigned reg, float weight, - const MRegisterInfo *MRI) { + const TargetRegisterInfo *TRI) { Weights[reg] += weight; - for (const unsigned* as = MRI->getAliasSet(reg); *as; ++as) + for (const unsigned* as = TRI->getAliasSet(reg); *as; ++as) Weights[*as] += weight; } @@ -525,7 +525,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) unsigned SrcReg, DstReg; if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) { unsigned Reg = 0; - if (MRegisterInfo::isPhysicalRegister(SrcReg)) + if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) Reg = SrcReg; else if (vrm_->isAssignedReg(SrcReg)) Reg = vrm_->getPhys(SrcReg); @@ -540,7 +540,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) for (IntervalPtrs::const_iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned Reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(Reg) && + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Can only allocate virtual registers!"); const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg); // If this is not in a related reg class to the register we're allocating, @@ -564,7 +564,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // conflict with it. Check to see if we conflict with it or any of its // aliases. SmallSet<unsigned, 8> RegAliases; - for (const unsigned *AS = mri_->getAliasSet(physReg); *AS; ++AS) + for (const unsigned *AS = tri_->getAliasSet(physReg); *AS; ++AS) RegAliases.insert(*AS); bool ConflictsWithFixed = false; @@ -626,7 +626,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // the free physical register and add this interval to the active // list. if (physReg) { - DOUT << mri_->getName(physReg) << '\n'; + DOUT << tri_->getName(physReg) << '\n'; vrm_->assignVirt2Phys(cur->reg, physReg); prt_->addRegUse(physReg); active_.push_back(std::make_pair(cur, cur->begin())); @@ -636,19 +636,19 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) DOUT << "no free registers\n"; // Compile the spill weights into an array that is better for scanning. - std::vector<float> SpillWeights(mri_->getNumRegs(), 0.0); + std::vector<float> SpillWeights(tri_->getNumRegs(), 0.0); for (std::vector<std::pair<unsigned, float> >::iterator I = SpillWeightsToAdd.begin(), E = SpillWeightsToAdd.end(); I != E; ++I) - updateSpillWeights(SpillWeights, I->first, I->second, mri_); + updateSpillWeights(SpillWeights, I->first, I->second, tri_); // for each interval in active, update spill weights. for (IntervalPtrs::const_iterator i = active_.begin(), e = active_.end(); i != e; ++i) { unsigned reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); reg = vrm_->getPhys(reg); - updateSpillWeights(SpillWeights, reg, i->first->weight, mri_); + updateSpillWeights(SpillWeights, reg, i->first->weight, tri_); } DOUT << "\tassigning stack slot at interval "<< *cur << ":\n"; @@ -674,7 +674,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) unsigned reg = *i; // No need to worry about if the alias register size < regsize of RC. // We are going to spill all registers that alias it anyway. - for (const unsigned* as = mri_->getAliasSet(reg); *as; ++as) { + for (const unsigned* as = tri_->getAliasSet(reg); *as; ++as) { if (minWeight > SpillWeights[*as]) { minWeight = SpillWeights[*as]; minReg = *as; @@ -688,7 +688,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) } DOUT << "\t\tregister with min weight: " - << mri_->getName(minReg) << " (" << minWeight << ")\n"; + << tri_->getName(minReg) << " (" << minWeight << ")\n"; // if the current has the minimum weight, we need to spill it and // add any added intervals back to unhandled, and restart @@ -719,13 +719,13 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // minimum weight, rollback to the interval with the earliest // start point and let the linear scan algorithm run again std::vector<LiveInterval*> added; - assert(MRegisterInfo::isPhysicalRegister(minReg) && + assert(TargetRegisterInfo::isPhysicalRegister(minReg) && "did not choose a register to spill?"); - BitVector toSpill(mri_->getNumRegs()); + BitVector toSpill(tri_->getNumRegs()); // We are going to spill minReg and all its aliases. toSpill[minReg] = true; - for (const unsigned* as = mri_->getAliasSet(minReg); *as; ++as) + for (const unsigned* as = tri_->getAliasSet(minReg); *as; ++as) toSpill[*as] = true; // the earliest start of a spilled interval indicates up to where @@ -742,7 +742,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) // mark our rollback point. for (IntervalPtrs::iterator i = active_.begin(); i != active_.end(); ++i) { unsigned reg = i->first->reg; - if (//MRegisterInfo::isVirtualRegister(reg) && + if (//TargetRegisterInfo::isVirtualRegister(reg) && toSpill[vrm_->getPhys(reg)] && cur->overlapsFrom(*i->first, i->second)) { DOUT << "\t\t\tspilling(a): " << *i->first << '\n'; @@ -755,7 +755,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) } for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end(); ++i){ unsigned reg = i->first->reg; - if (//MRegisterInfo::isVirtualRegister(reg) && + if (//TargetRegisterInfo::isVirtualRegister(reg) && toSpill[vrm_->getPhys(reg)] && cur->overlapsFrom(*i->first, i->second-1)) { DOUT << "\t\t\tspilling(i): " << *i->first << '\n'; @@ -785,19 +785,19 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) IntervalPtrs::iterator it; if ((it = FindIntervalInVector(active_, i)) != active_.end()) { active_.erase(it); - assert(!MRegisterInfo::isPhysicalRegister(i->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(i->reg)); if (!spilled.count(i->reg)) unhandled_.push(i); prt_->delRegUse(vrm_->getPhys(i->reg)); vrm_->clearVirt(i->reg); } else if ((it = FindIntervalInVector(inactive_, i)) != inactive_.end()) { inactive_.erase(it); - assert(!MRegisterInfo::isPhysicalRegister(i->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(i->reg)); if (!spilled.count(i->reg)) unhandled_.push(i); vrm_->clearVirt(i->reg); } else { - assert(MRegisterInfo::isVirtualRegister(i->reg) && + assert(TargetRegisterInfo::isVirtualRegister(i->reg) && "Can only allocate virtual registers!"); vrm_->clearVirt(i->reg); unhandled_.push(i); @@ -824,7 +824,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) HI->expiredAt(cur->beginNumber())) { DOUT << "\t\t\tundo changes for: " << *HI << '\n'; active_.push_back(std::make_pair(HI, HI->begin())); - assert(!MRegisterInfo::isPhysicalRegister(HI->reg)); + assert(!TargetRegisterInfo::isPhysicalRegister(HI->reg)); prt_->addRegUse(vrm_->getPhys(HI->reg)); } } @@ -837,7 +837,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) /// getFreePhysReg - return a free physical register for this virtual register /// interval if we have one, otherwise return 0. unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { - std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0); + std::vector<unsigned> inactiveCounts(tri_->getNumRegs(), 0); unsigned MaxInactiveCount = 0; const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg); @@ -846,7 +846,7 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end(); i != e; ++i) { unsigned reg = i->first->reg; - assert(MRegisterInfo::isVirtualRegister(reg) && + assert(TargetRegisterInfo::isVirtualRegister(reg) && "Can only allocate virtual registers!"); // If this is not in a related reg class to the register we're allocating, @@ -867,11 +867,11 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) { if (cur->preference) if (prt_->isRegAvail(cur->preference)) { DOUT << "\t\tassigned the preferred register: " - << mri_->getName(cur->preference) << "\n"; + << tri_->getName(cur->preference) << "\n"; return cur->preference; } else DOUT << "\t\tunable to assign the preferred register: " - << mri_->getName(cur->preference) << "\n"; + << tri_->getName(cur->preference) << "\n"; // Scan for the first available register. TargetRegisterClass::iterator I = RC->allocation_order_begin(*mf_); diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index 477cc4b..12064a9 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -49,7 +49,7 @@ namespace { private: const TargetMachine *TM; MachineFunction *MF; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; // StackSlotForVirtReg - Maps virtual regs to the frame index where these @@ -91,7 +91,7 @@ namespace { Virt2LastUseMap; std::pair<MachineInstr*,unsigned>& getVirtRegLastUse(unsigned Reg) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); return Virt2LastUseMap[Reg]; } @@ -103,8 +103,8 @@ namespace { BitVector VirtRegModified; void markVirtRegModified(unsigned Reg, bool Val = true) { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - Reg -= MRegisterInfo::FirstVirtualRegister; + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + Reg -= TargetRegisterInfo::FirstVirtualRegister; if (Val) VirtRegModified.set(Reg); else @@ -112,10 +112,10 @@ namespace { } bool isVirtRegModified(unsigned Reg) const { - assert(MRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); - assert(Reg - MRegisterInfo::FirstVirtualRegister < VirtRegModified.size() + assert(TargetRegisterInfo::isVirtualRegister(Reg) && "Illegal VirtReg!"); + assert(Reg - TargetRegisterInfo::FirstVirtualRegister < VirtRegModified.size() && "Illegal virtual register!"); - return VirtRegModified[Reg - MRegisterInfo::FirstVirtualRegister]; + return VirtRegModified[Reg - TargetRegisterInfo::FirstVirtualRegister]; } void AddToPhysRegsUseOrder(unsigned Reg) { @@ -167,7 +167,7 @@ namespace { /// bool areRegsEqual(unsigned R1, unsigned R2) const { if (R1 == R2) return true; - for (const unsigned *AliasSet = MRI->getAliasSet(R2); + for (const unsigned *AliasSet = TRI->getAliasSet(R2); *AliasSet; ++AliasSet) { if (*AliasSet == R1) return true; } @@ -286,7 +286,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB, assert(VirtReg && "Spilling a physical register is illegal!" " Must not have appropriate kill for the register or use exists beyond" " the intended one."); - DOUT << " Spilling register " << MRI->getName(PhysReg) + DOUT << " Spilling register " << TRI->getName(PhysReg) << " containing %reg" << VirtReg; const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); @@ -338,7 +338,7 @@ void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I, } else { // If the selected register aliases any other registers, we must make // sure that one of the aliases isn't alive. - for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); + for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register. PhysRegsUsed[*AliasSet] != -2) // If allocatable. @@ -371,7 +371,7 @@ bool RALocal::isPhysRegAvailable(unsigned PhysReg) const { // If the selected register aliases any other allocated registers, it is // not free! - for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); + for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use? return false; // Can't use this reg then. @@ -434,7 +434,7 @@ unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I, } else { // If one of the registers aliased to the current register is // compatible, use it. - for (const unsigned *AliasIt = MRI->getAliasSet(R); + for (const unsigned *AliasIt = TRI->getAliasSet(R); *AliasIt; ++AliasIt) { if (RC->contains(*AliasIt) && // If this is pinned down for some reason, don't use it. For @@ -507,7 +507,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI, markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded DOUT << " Reloading %reg" << VirtReg << " into " - << MRI->getName(PhysReg) << "\n"; + << TRI->getName(PhysReg) << "\n"; // Add move instruction(s) const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo(); @@ -561,7 +561,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { MF->getRegInfo().setPhysRegUsed(Reg); PhysRegsUsed[Reg] = 0; // It is free and reserved now AddToPhysRegsUseOrder(Reg); - for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); + for (const unsigned *AliasSet = TRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { AddToPhysRegsUseOrder(*AliasSet); @@ -578,9 +578,9 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { const TargetInstrDesc &TID = MI->getDesc(); DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI; DOUT << " Regs have values: "; - for (unsigned i = 0; i != MRI->getNumRegs(); ++i) + for (unsigned i = 0; i != TRI->getNumRegs(); ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) - DOUT << "[" << MRI->getName(i) + DOUT << "[" << TRI->getName(i) << ",%reg" << PhysRegsUsed[i] << "] "; DOUT << "\n"); @@ -616,7 +616,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineOperand& MO = MI->getOperand(i); // here we are looking for only used operands (never def&use) if (MO.isRegister() && !MO.isDef() && MO.getReg() && !MO.isImplicit() && - MRegisterInfo::isVirtualRegister(MO.getReg())) + TargetRegisterInfo::isVirtualRegister(MO.getReg())) MI = reloadVirtReg(MBB, MI, i); } @@ -627,7 +627,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = Kills.size(); i != e; ++i) { unsigned VirtReg = Kills[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { // If the virtual register was never materialized into a register, it // might not be in the map, but it won't hurt to zero it out anyway. unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); @@ -642,14 +642,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { } if (PhysReg) { - DOUT << " Last use of " << MRI->getName(PhysReg) + DOUT << " Last use of " << TRI->getName(PhysReg) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = MRI->getSubRegisters(PhysReg); + for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { DOUT << " Last use of " - << MRI->getName(*AliasSet) + << TRI->getName(*AliasSet) << "[%reg" << VirtReg <<"], removing it from live set\n"; removePhysReg(*AliasSet); } @@ -662,7 +662,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() && - MRegisterInfo::isPhysicalRegister(MO.getReg())) { + TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP. // These are extra physical register defs when a sub-register @@ -675,7 +675,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { PhysRegsUsed[Reg] = 0; // It is free and reserved now AddToPhysRegsUseOrder(Reg); - for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); + for (const unsigned *AliasSet = TRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { MF->getRegInfo().setPhysRegUsed(*AliasSet); @@ -697,7 +697,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { PhysRegsUsed[Reg] = 0; // It is free and reserved now } MF->getRegInfo().setPhysRegUsed(Reg); - for (const unsigned *AliasSet = MRI->getSubRegisters(Reg); + for (const unsigned *AliasSet = TRI->getSubRegisters(Reg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { AddToPhysRegsUseOrder(*AliasSet); @@ -723,7 +723,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand& MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned DestVirtReg = MO.getReg(); unsigned DestPhysReg; @@ -743,7 +743,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { for (unsigned i = 0, e = DeadDefs.size(); i != e; ++i) { unsigned VirtReg = DeadDefs[i]; unsigned PhysReg = VirtReg; - if (MRegisterInfo::isVirtualRegister(VirtReg)) { + if (TargetRegisterInfo::isVirtualRegister(VirtReg)) { unsigned &PhysRegSlot = getVirt2PhysRegMapSlot(VirtReg); PhysReg = PhysRegSlot; assert(PhysReg != 0); @@ -754,14 +754,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { } if (PhysReg) { - DOUT << " Register " << MRI->getName(PhysReg) + DOUT << " Register " << TRI->getName(PhysReg) << " [%reg" << VirtReg << "] is never used, removing it frame live list\n"; removePhysReg(PhysReg); - for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg); + for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg); *AliasSet; ++AliasSet) { if (PhysRegsUsed[*AliasSet] != -2) { - DOUT << " Register " << MRI->getName(*AliasSet) + DOUT << " Register " << TRI->getName(*AliasSet) << " [%reg" << *AliasSet << "] is never used, removing it frame live list\n"; removePhysReg(*AliasSet); @@ -779,7 +779,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineBasicBlock::iterator MI = MBB.getFirstTerminator(); // Spill all physical registers holding virtual registers now. - for (unsigned i = 0, e = MRI->getNumRegs(); i != e; ++i) + for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2) if (unsigned VirtReg = PhysRegsUsed[i]) spillVirtReg(MBB, MI, VirtReg, i); @@ -789,7 +789,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) { #if 0 // This checking code is very expensive. bool AllOk = true; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) if (unsigned PR = Virt2PhysRegMap[i]) { cerr << "Register still mapped: " << i << " -> " << PR << "\n"; @@ -811,16 +811,16 @@ bool RALocal::runOnMachineFunction(MachineFunction &Fn) { DOUT << "Machine Function " << "\n"; MF = &Fn; TM = &Fn.getTarget(); - MRI = TM->getRegisterInfo(); + TRI = TM->getRegisterInfo(); TII = TM->getInstrInfo(); - PhysRegsUsed.assign(MRI->getNumRegs(), -1); + PhysRegsUsed.assign(TRI->getNumRegs(), -1); // At various places we want to efficiently check to see whether a register // is allocatable. To handle this, we mark all unallocatable registers as // being pinned down, permanently. { - BitVector Allocable = MRI->getAllocatableSet(Fn); + BitVector Allocable = TRI->getAllocatableSet(Fn); for (unsigned i = 0, e = Allocable.size(); i != e; ++i) if (!Allocable[i]) PhysRegsUsed[i] = -2; // Mark the reg unallocable. @@ -831,7 +831,7 @@ bool RALocal::runOnMachineFunction(MachineFunction &Fn) { unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg(); Virt2PhysRegMap.grow(LastVirtReg); Virt2LastUseMap.grow(LastVirtReg); - VirtRegModified.resize(LastVirtReg+1-MRegisterInfo::FirstVirtualRegister); + VirtRegModified.resize(LastVirtReg+1-TargetRegisterInfo::FirstVirtualRegister); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp index a4743ed..d65136a 100644 --- a/lib/CodeGen/RegAllocSimple.cpp +++ b/lib/CodeGen/RegAllocSimple.cpp @@ -44,7 +44,7 @@ namespace { private: MachineFunction *MF; const TargetMachine *TM; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where // these values are spilled @@ -169,7 +169,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { // Made to combat the incorrect allocation of r2 = add r1, r1 std::map<unsigned, unsigned> Virt2PhysRegMap; - RegsUsed.resize(MRI->getNumRegs()); + RegsUsed.resize(TRI->getNumRegs()); // This is a preliminary pass that will invalidate any registers that are // used by the instruction (including implicit uses). @@ -192,7 +192,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) { MachineOperand &op = MI->getOperand(i); if (op.isRegister() && op.getReg() && - MRegisterInfo::isVirtualRegister(op.getReg())) { + TargetRegisterInfo::isVirtualRegister(op.getReg())) { unsigned virtualReg = (unsigned) op.getReg(); DOUT << "op: " << op << "\n"; DOUT << "\t inst[" << i << "]: "; @@ -239,7 +239,7 @@ bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) { DOUT << "Machine Function\n"; MF = &Fn; TM = &MF->getTarget(); - MRI = TM->getRegisterInfo(); + TRI = TM->getRegisterInfo(); // Loop over all of the basic blocks, eliminating virtual register references for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index fb53d5e..9d25d2a 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -16,7 +16,7 @@ #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Pass.h" using namespace llvm; diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index aeed72c..839c185 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -19,7 +19,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineInstr.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/STLExtras.h" diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp index 337c7fd..591e9aa 100644 --- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp +++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp @@ -14,7 +14,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -22,11 +22,11 @@ using namespace llvm; CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm, SmallVector<CCValAssign, 16> &locs) : CallingConv(CC), IsVarArg(isVarArg), TM(tm), - MRI(*TM.getRegisterInfo()), Locs(locs) { + TRI(*TM.getRegisterInfo()), Locs(locs) { // No stack is used. StackOffset = 0; - UsedRegs.resize(MRI.getNumRegs()); + UsedRegs.resize(TRI.getNumRegs()); } // HandleByVal - Allocate a stack slot large enough to pass an argument by @@ -53,7 +53,7 @@ void CCState::HandleByVal(unsigned ValNo, MVT::ValueType ValVT, void CCState::MarkAllocated(unsigned Reg) { UsedRegs[Reg/32] |= 1 << (Reg&31); - if (const unsigned *RegAliases = MRI.getAliasSet(Reg)) + if (const unsigned *RegAliases = TRI.getAliasSet(Reg)) for (; (Reg = *RegAliases); ++RegAliases) UsedRegs[Reg/32] |= 1 << (Reg&31); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 043f7c1..a35c9ef 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -32,7 +32,7 @@ ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) { TII = TM.getInstrInfo(); MF = &DAG.getMachineFunction(); - MRI = TM.getRegisterInfo(); + TRI = TM.getRegisterInfo(); ConstPool = BB->getParent()->getConstantPool(); } @@ -40,14 +40,14 @@ ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb, /// a specified operand is a physical register dependency. If so, returns the /// register and the cost of copying the register. static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op, - const MRegisterInfo *MRI, + const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) { if (Op != 2 || Use->getOpcode() != ISD::CopyToReg) return; unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) + if (TargetRegisterInfo::isVirtualRegister(Reg)) return; unsigned ResNo = Use->getOperand(2).ResNo; @@ -57,7 +57,7 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *Use, unsigned Op, II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { PhysReg = Reg; const TargetRegisterClass *RC = - MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg); + TRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg); Cost = RC->getCopyCost(); } } @@ -185,7 +185,7 @@ void ScheduleDAG::BuildSchedUnits() { unsigned PhysReg = 0; int Cost = 1; // Determine if this is a physical register dependency. - CheckForPhysRegDependency(OpN, N, i, MRI, TII, PhysReg, Cost); + CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost); SU->addPred(OpSU, isChain, false, PhysReg, Cost); } } @@ -302,7 +302,7 @@ unsigned ScheduleDAG::CountMemOperands(SDNode *Node) { } static const TargetRegisterClass *getInstrOperandRegClass( - const MRegisterInfo *MRI, + const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, const TargetInstrDesc &II, unsigned Op) { @@ -312,14 +312,14 @@ static const TargetRegisterClass *getInstrOperandRegClass( } if (II.OpInfo[Op].isLookupPtrRegClass()) return TII->getPointerRegClass(); - return MRI->getRegClass(II.OpInfo[Op].RegClass); + return TRI->getRegClass(II.OpInfo[Op].RegClass); } void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, unsigned InstanceNo, unsigned SrcReg, DenseMap<SDOperand, unsigned> &VRBaseMap) { unsigned VRBase = 0; - if (MRegisterInfo::isVirtualRegister(SrcReg)) { + if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { // Just use the input register directly! if (InstanceNo > 0) VRBaseMap.erase(SDOperand(Node, ResNo)); @@ -339,7 +339,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, Use->getOperand(2).Val == Node && Use->getOperand(2).ResNo == ResNo) { unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(DestReg)) { + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { VRBase = DestReg; Match = false; } else if (DestReg != SrcReg) @@ -364,7 +364,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo, if (VRBase) TRC = RegInfo.getRegClass(VRBase); else - TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); + TRC = TRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg); // If all uses are reading from the src physical register and copying the // register is either impossible or very expensive, then don't create a copy. @@ -398,7 +398,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, Use->getOperand(2).Val == Node && Use->getOperand(2).ResNo == i) { unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(Reg)) { + if (TargetRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; MI->addOperand(MachineOperand::CreateReg(Reg, true)); break; @@ -409,7 +409,7 @@ void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, // Create the result registers for this node and add the result regs to // the machine instruction. if (VRBase == 0) { - const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i); + const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TII, II, i); assert(RC && "Isn't a register operand!"); VRBase = RegInfo.createVirtualRegister(RC); MI->addOperand(MachineOperand::CreateReg(VRBase, true)); @@ -453,10 +453,10 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef)); // Verify that it is right. - assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); + assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); if (II) { const TargetRegisterClass *RC = - getInstrOperandRegClass(MRI, TII, *II, IIOpNum); + getInstrOperandRegClass(TRI, TII, *II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg); if (VRC != RC) { @@ -517,10 +517,10 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, MI->addOperand(MachineOperand::CreateReg(VReg, false)); // Verify that it is right. - assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); + assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); if (II) { const TargetRegisterClass *RC = - getInstrOperandRegClass(MRI, TII, *II, IIOpNum); + getInstrOperandRegClass(TRI, TII, *II, IIOpNum); assert(RC && "Don't have operand info for this instruction!"); assert(RegInfo.getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"); @@ -538,7 +538,8 @@ static const TargetRegisterClass *getSubRegisterRegClass( const TargetRegisterClass *TRC, unsigned SubIdx) { // Pick the register class of the subregister - MRegisterInfo::regclass_iterator I = TRC->subregclasses_begin() + SubIdx-1; + TargetRegisterInfo::regclass_iterator I = + TRC->subregclasses_begin() + SubIdx-1; assert(I < TRC->subregclasses_end() && "Invalid subregister index for register class"); return *I; @@ -549,7 +550,7 @@ static const TargetRegisterClass *getSuperregRegisterClass( unsigned SubIdx, MVT::ValueType VT) { // Pick the register class of the superegister for this type - for (MRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), + for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), E = TRC->superregclasses_end(); I != E; ++I) if ((*I)->hasType(VT) && getSubRegisterRegClass(*I, SubIdx) == TRC) return *I; @@ -572,7 +573,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, if (Use->getOpcode() == ISD::CopyToReg && Use->getOperand(2).Val == Node) { unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(DestReg)) { + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { VRBase = DestReg; break; } @@ -638,7 +639,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node, if (Use->getOpcode() == ISD::CopyToReg && Use->getOperand(2).Val == Node) { unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); - if (MRegisterInfo::isVirtualRegister(DestReg)) { + if (TargetRegisterInfo::isVirtualRegister(DestReg)) { VRBase = DestReg; break; } @@ -770,11 +771,11 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo, if (InReg != DestReg) {// Coalesced away the copy? const TargetRegisterClass *TRC = 0; // Get the target register class - if (MRegisterInfo::isVirtualRegister(InReg)) + if (TargetRegisterInfo::isVirtualRegister(InReg)) TRC = RegInfo.getRegClass(InReg); else TRC = - MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), + TRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(), InReg); TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC); } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index 42d54f6..3ae5e13 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -22,7 +22,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 8681844..eae19b9 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -18,7 +18,7 @@ #define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" @@ -106,8 +106,8 @@ private: void ScheduleDAGRRList::Schedule() { DOUT << "********** List Scheduling **********\n"; - LiveRegDefs.resize(MRI->getNumRegs(), NULL); - LiveRegCycles.resize(MRI->getNumRegs(), 0); + LiveRegDefs.resize(TRI->getNumRegs(), NULL); + LiveRegCycles.resize(TRI->getNumRegs(), 0); // Build scheduling units. BuildSchedUnits(); @@ -651,7 +651,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (RegAdded.insert(Reg)) LRegs.push_back(Reg); } - for (const unsigned *Alias = MRI->getAliasSet(Reg); + for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != I->Dep) { if (RegAdded.insert(*Alias)) @@ -672,7 +672,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (RegAdded.insert(*Reg)) LRegs.push_back(*Reg); } - for (const unsigned *Alias = MRI->getAliasSet(*Reg); + for (const unsigned *Alias = TRI->getAliasSet(*Reg); *Alias; ++Alias) if (LiveRegs.count(*Alias) && LiveRegDefs[*Alias] != SU) { if (RegAdded.insert(*Alias)) @@ -768,8 +768,8 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { // Issue expensive cross register class copies. MVT::ValueType VT = getPhysicalRegisterVT(LRDef->Node, Reg, TII); const TargetRegisterClass *RC = - MRI->getPhysicalRegisterRegClass(VT, Reg); - const TargetRegisterClass *DestRC = MRI->getCrossCopyRegClass(RC); + TRI->getPhysicalRegisterRegClass(VT, Reg); + const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); if (!DestRC) { assert(false && "Don't know how to copy this physical register!"); abort(); @@ -1063,11 +1063,11 @@ namespace { std::vector<unsigned> SethiUllmanNumbers; const TargetInstrInfo *TII; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; public: explicit BURegReductionPriorityQueue(const TargetInstrInfo *tii, - const MRegisterInfo *mri) - : TII(tii), MRI(mri) {} + const TargetRegisterInfo *tri) + : TII(tii), TRI(tri) {} void initNodes(DenseMap<SDNode*, std::vector<SUnit*> > &sumap, std::vector<SUnit> &sunits) { @@ -1320,7 +1320,7 @@ static bool hasCopyToRegUse(SUnit *SU) { /// physical register def. static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, const TargetInstrInfo *TII, - const MRegisterInfo *MRI) { + const TargetRegisterInfo *TRI) { SDNode *N = SuccSU->Node; unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs(); const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs(); @@ -1337,7 +1337,7 @@ static bool canClobberPhysRegDefs(SUnit *SuccSU, SUnit *SU, unsigned Reg = ImpDefs[i - NumDefs]; for (;*SUImpDefs; ++SUImpDefs) { unsigned SUReg = *SUImpDefs; - if (MRI->regsOverlap(Reg, SUReg)) + if (TRI->regsOverlap(Reg, SUReg)) return true; } } @@ -1388,7 +1388,7 @@ void BURegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() { // Don't constrain nodes with physical register defs if the // predecessor can clobber them. if (SuccSU->hasPhysRegDefs) { - if (canClobberPhysRegDefs(SuccSU, SU, TII, MRI)) + if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } // Don't constraint extract_subreg / insert_subreg these may be @@ -1580,9 +1580,9 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, MachineBasicBlock *BB) { const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo(); - const MRegisterInfo *MRI = DAG->getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo(); return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, - new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, MRI)); + new BURegReductionPriorityQueue<bu_ls_rr_sort>(TII, TRI)); } llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index bead077..c0351bb 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -23,7 +23,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetInstrInfo.h" @@ -4051,7 +4051,8 @@ void SDNode::dump(const SelectionDAG *G) const { cerr << LBB->getName() << " "; cerr << (const void*)BBDN->getBasicBlock() << ">"; } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) { - if (G && R->getReg() && MRegisterInfo::isPhysicalRegister(R->getReg())) { + if (G && R->getReg() && + TargetRegisterInfo::isPhysicalRegister(R->getReg())) { cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg()); } else { cerr << " #" << R->getReg(); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 55231f3..9e91e9f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -35,7 +35,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -3148,11 +3148,12 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, /// register class for the register. Otherwise, return null. static const TargetRegisterClass * isAllocatableRegister(unsigned Reg, MachineFunction &MF, - const TargetLowering &TLI, const MRegisterInfo *MRI) { + const TargetLowering &TLI, + const TargetRegisterInfo *TRI) { MVT::ValueType FoundVT = MVT::Other; const TargetRegisterClass *FoundRC = 0; - for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), - E = MRI->regclass_end(); RCI != E; ++RCI) { + for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), + E = TRI->regclass_end(); RCI != E; ++RCI) { MVT::ValueType ThisVT = MVT::Other; const TargetRegisterClass *RC = *RCI; @@ -3416,7 +3417,7 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, OpInfo.ConstraintVT); } - const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); unsigned NumAllocated = 0; for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { unsigned Reg = RegClassRegs[i]; @@ -3431,7 +3432,7 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, // Check to see if this register is allocatable (i.e. don't give out the // stack pointer). if (RC == 0) { - RC = isAllocatableRegister(Reg, MF, TLI, MRI); + RC = isAllocatableRegister(Reg, MF, TLI, TRI); if (!RC) { // Couldn't allocate this register. // Reset NumAllocated to make sure we return consecutive registers. NumAllocated = 0; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 719b949..2d6d040 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -18,7 +18,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/GraphWriter.h" #include "llvm/ADT/StringExtras.h" @@ -132,7 +132,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node, //Op += " " + (const void*)BBDN->getBasicBlock(); } else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) { if (G && R->getReg() != 0 && - MRegisterInfo::isPhysicalRegister(R->getReg())) { + TargetRegisterInfo::isPhysicalRegister(R->getReg())) { Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R->getReg()); } else { Op += " #" + utostr(R->getReg()); diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 40fb315..c3e3dae 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -15,7 +15,7 @@ #include "llvm/Target/TargetSubtarget.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/DerivedTypes.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/ADT/StringExtras.h" @@ -1614,8 +1614,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, std::string RegName(Constraint.begin()+1, Constraint.end()-1); // Figure out which register class contains this reg. - const MRegisterInfo *RI = TM.getRegisterInfo(); - for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), + const TargetRegisterInfo *RI = TM.getRegisterInfo(); + for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), E = RI->regclass_end(); RCI != E; ++RCI) { const TargetRegisterClass *RC = *RCI; diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index d1b65c4..6035f92 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -137,17 +137,17 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // If a live interval is a physical register, conservatively check if any // of its sub-registers is overlapping the live interval of the virtual // register. If so, do not coalesce. - if (MRegisterInfo::isPhysicalRegister(IntB.reg) && - *mri_->getSubRegisters(IntB.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR) + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) && + *tri_->getSubRegisters(IntB.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } } - DOUT << "\nExtending: "; IntB.print(DOUT, mri_); + DOUT << "\nExtending: "; IntB.print(DOUT, tri_); unsigned FillerStart = ValLR->end, FillerEnd = BLR->start; // We are about to delete CopyMI, so need to remove it as the 'instruction @@ -163,9 +163,9 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // If the IntB live range is assigned to a physical register, and if that // physreg has aliases, - if (MRegisterInfo::isPhysicalRegister(IntB.reg)) { + if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) { // Update the liveintervals of sub-registers. - for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) { + for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) { LiveInterval &AliasLI = li_->getInterval(*AS); AliasLI.addRange(LiveRange(FillerStart, FillerEnd, AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator()))); @@ -175,7 +175,7 @@ bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, // Okay, merge "B1" into the same value number as "B0". if (BValNo != ValLR->valno) IntB.MergeValueNumberInto(BValNo, ValLR->valno); - DOUT << " result = "; IntB.print(DOUT, mri_); + DOUT << " result = "; IntB.print(DOUT, tri_); DOUT << "\n"; // If the source instruction was killing the source register before the @@ -249,8 +249,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { return false; // Not coalescable. } - bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg); - bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg); + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg); + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg); // If they are both physical registers, we cannot join them. if (SrcIsPhys && DstIsPhys) { @@ -275,15 +275,15 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { if (SrcIsPhys) // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be // coalesced with AX. - repSrcReg = mri_->getSubReg(repSrcReg, SubIdx); + repSrcReg = tri_->getSubReg(repSrcReg, SubIdx); else if (DstIsPhys) { // If this is a extract_subreg where dst is a physical register, e.g. // cl = EXTRACT_SUBREG reg1024, 1 // then create and update the actual physical register allocated to RHS. const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg); - for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg); + for (const unsigned *SRs = tri_->getSuperRegisters(repDstReg); unsigned SR = *SRs; ++SRs) { - if (repDstReg == mri_->getSubReg(SR, SubIdx) && + if (repDstReg == tri_->getSubReg(SR, SubIdx) && RC->contains(SR)) { RealDstReg = SR; break; @@ -298,13 +298,13 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { if (li_->hasInterval(RealDstReg) && RHS.overlaps(li_->getInterval(RealDstReg))) { DOUT << "Interfere with register "; - DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_)); + DEBUG(li_->getInterval(RealDstReg).print(DOUT, tri_)); return false; // Not coalescable } - for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR) + for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR) if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; // Not coalescable } } else { @@ -340,8 +340,8 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg && "Register mapping is horribly broken!"); - DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_); - DOUT << " and "; DstInt.print(DOUT, mri_); + DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_); + DOUT << " and "; DstInt.print(DOUT, tri_); DOUT << ": "; // Check if it is necessary to propagate "isDead" property before intervals @@ -421,7 +421,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { if (isDead) { // Result of the copy is dead. Propagate this property. if (SrcStart == 0) { - assert(MRegisterInfo::isPhysicalRegister(repSrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(repSrcReg) && "Live-in must be a physical register!"); // Live-in to the function but dead. Remove it from entry live-in set. // JoinIntervals may end up swapping the two intervals. @@ -462,13 +462,13 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { std::swap(repSrcReg, repDstReg); std::swap(ResSrcInt, ResDstInt); } - assert(MRegisterInfo::isVirtualRegister(repSrcReg) && + assert(TargetRegisterInfo::isVirtualRegister(repSrcReg) && "LiveInterval::join didn't work right!"); // If we're about to merge live ranges into a physical register live range, // we have to update any aliased register's live ranges to indicate that they // have clobbered values for this range. - if (MRegisterInfo::isPhysicalRegister(repDstReg)) { + if (TargetRegisterInfo::isPhysicalRegister(repDstReg)) { // Unset unnecessary kills. if (!ResDstInt->containsOneValue()) { for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(), @@ -500,7 +500,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { } // Update the liveintervals of sub-registers. - for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS) + for (const unsigned *AS = tri_->getSubRegisters(repDstReg); *AS; ++AS) li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt, li_->getVNInfoAllocator()); } else { @@ -511,9 +511,9 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { } // Remember these liveintervals have been joined. - JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister); - if (MRegisterInfo::isVirtualRegister(repDstReg)) - JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister); + JoinedLIs.set(repSrcReg - TargetRegisterInfo::FirstVirtualRegister); + if (TargetRegisterInfo::isVirtualRegister(repDstReg)) + JoinedLIs.set(repDstReg - TargetRegisterInfo::FirstVirtualRegister); if (isExtSubReg && !SrcIsPhys && !DstIsPhys) { if (!Swapped) { @@ -544,7 +544,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) { } } - DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_); + DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_); DOUT << "\n"; // repSrcReg is guarateed to be the register whose live interval that is @@ -763,20 +763,20 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, // If a live interval is a physical register, conservatively check if any // of its sub-registers is overlapping the live interval of the virtual // register. If so, do not coalesce. - if (MRegisterInfo::isPhysicalRegister(LHS.reg) && - *mri_->getSubRegisters(LHS.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR) + if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) && + *tri_->getSubRegisters(LHS.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR) if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } - } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) && - *mri_->getSubRegisters(RHS.reg)) { - for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR) + } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) && + *tri_->getSubRegisters(RHS.reg)) { + for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR) if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) { DOUT << "Interfere with sub-register "; - DEBUG(li_->getInterval(*SR).print(DOUT, mri_)); + DEBUG(li_->getInterval(*SR).print(DOUT, tri_)); return false; } } @@ -797,7 +797,7 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, // If RHS is not defined as a copy from the LHS, we can use simpler and // faster checks to see if the live ranges are coalescable. This joiner // can't swap the LHS/RHS intervals though. - if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) { + if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { return SimpleJoin(LHS, RHS); } else { RHSValNoInfo = RHSValNoInfo0; @@ -988,8 +988,8 @@ bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, // If we get here, we know that we can coalesce the live ranges. Ask the // intervals to coalesce themselves now. if ((RHS.ranges.size() > LHS.ranges.size() && - MRegisterInfo::isVirtualRegister(LHS.reg)) || - MRegisterInfo::isPhysicalRegister(RHS.reg)) { + TargetRegisterInfo::isVirtualRegister(LHS.reg)) || + TargetRegisterInfo::isPhysicalRegister(RHS.reg)) { RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo); Swapped = true; } else { @@ -1030,11 +1030,11 @@ bool CopyRecSort::operator()(CopyRec left, CopyRec right) const { return false; else if (left.isBackEdge == right.isBackEdge) { // Join virtuals to physical registers first. - bool LDstIsPhys = MRegisterInfo::isPhysicalRegister(left.DstReg); - bool LSrcIsPhys = MRegisterInfo::isPhysicalRegister(left.SrcReg); + bool LDstIsPhys = TargetRegisterInfo::isPhysicalRegister(left.DstReg); + bool LSrcIsPhys = TargetRegisterInfo::isPhysicalRegister(left.SrcReg); bool LIsPhys = LDstIsPhys || LSrcIsPhys; - bool RDstIsPhys = MRegisterInfo::isPhysicalRegister(right.DstReg); - bool RSrcIsPhys = MRegisterInfo::isPhysicalRegister(right.SrcReg); + bool RDstIsPhys = TargetRegisterInfo::isPhysicalRegister(right.DstReg); + bool RSrcIsPhys = TargetRegisterInfo::isPhysicalRegister(right.SrcReg); bool RIsPhys = RDstIsPhys || RSrcIsPhys; if (LIsPhys && !RIsPhys) return false; @@ -1082,8 +1082,8 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB, unsigned repSrcReg = rep(SrcReg); unsigned repDstReg = rep(DstReg); - bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg); - bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg); + bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(repSrcReg); + bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(repDstReg); if (NewHeuristic) { JoinQueue->push(CopyRec(Inst, SrcReg, DstReg, LoopDepth, isBackEdgeCopy(Inst, DstReg))); @@ -1198,7 +1198,7 @@ void SimpleRegisterCoalescing::joinIntervals() { // unnecessary kills. int RegNum = JoinedLIs.find_first(); while (RegNum != -1) { - unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister; + unsigned Reg = RegNum + TargetRegisterInfo::FirstVirtualRegister; unsigned repReg = rep(Reg); LiveInterval &LI = li_->getInterval(repReg); LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg); @@ -1233,15 +1233,15 @@ bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB) const { // Get the register classes for the first reg. - if (MRegisterInfo::isPhysicalRegister(RegA)) { - assert(MRegisterInfo::isVirtualRegister(RegB) && + if (TargetRegisterInfo::isPhysicalRegister(RegA)) { + assert(TargetRegisterInfo::isVirtualRegister(RegB) && "Shouldn't consider two physregs!"); return !mf_->getRegInfo().getRegClass(RegB)->contains(RegA); } // Compare against the regclass for the second reg. const TargetRegisterClass *RegClass = mf_->getRegInfo().getRegClass(RegA); - if (MRegisterInfo::isVirtualRegister(RegB)) + if (TargetRegisterInfo::isVirtualRegister(RegB)) return RegClass != mf_->getRegInfo().getRegClass(RegB); else return !RegClass->contains(RegB); @@ -1268,7 +1268,7 @@ SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isUse() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) { + tri_->regsOverlap(rep(MO.getReg()), Reg)) { MOU = &MO; return MI; } @@ -1288,7 +1288,7 @@ MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) + tri_->regsOverlap(rep(MO.getReg()), Reg)) return &MO; } return NULL; @@ -1301,7 +1301,7 @@ void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isKill() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) + tri_->regsOverlap(rep(MO.getReg()), Reg)) MO.setIsKill(false); } } @@ -1325,7 +1325,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End, for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isKill() && MO.getReg() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) { + tri_->regsOverlap(rep(MO.getReg()), Reg)) { MO.setIsKill(false); } } @@ -1340,15 +1340,15 @@ bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && - mri_->regsOverlap(rep(MO.getReg()), Reg)) + tri_->regsOverlap(rep(MO.getReg()), Reg)) return true; } return false; } void SimpleRegisterCoalescing::printRegName(unsigned reg) const { - if (MRegisterInfo::isPhysicalRegister(reg)) - cerr << mri_->getName(reg); + if (TargetRegisterInfo::isPhysicalRegister(reg)) + cerr << tri_->getName(reg); else cerr << "%reg" << reg; } @@ -1374,7 +1374,7 @@ static bool isZeroLengthInterval(LiveInterval *li) { bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { mf_ = &fn; tm_ = &fn.getTarget(); - mri_ = tm_->getRegisterInfo(); + tri_ = tm_->getRegisterInfo(); tii_ = tm_->getInstrInfo(); li_ = &getAnalysis<LiveIntervals>(); lv_ = &getAnalysis<LiveVariables>(); @@ -1384,11 +1384,11 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { << "********** Function: " << ((Value*)mf_->getFunction())->getName() << '\n'; - allocatableRegs_ = mri_->getAllocatableSet(fn); - for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(), - E = mri_->regclass_end(); I != E; ++I) + allocatableRegs_ = tri_->getAllocatableSet(fn); + for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), + E = tri_->regclass_end(); I != E; ++I) allocatableRCRegs_.insert(std::make_pair(*I, - mri_->getAllocatableSet(fn, *I))); + tri_->getAllocatableSet(fn, *I))); MachineRegisterInfo &RegInfo = mf_->getRegInfo(); r2rMap_.grow(RegInfo.getLastVirtReg()); @@ -1400,7 +1400,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { joinIntervals(); DOUT << "********** INTERVALS POST JOINING **********\n"; for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){ - I->second.print(DOUT, mri_); + I->second.print(DOUT, tri_); DOUT << "\n"; } @@ -1454,13 +1454,13 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) { const MachineOperand &mop = mii->getOperand(i); if (mop.isRegister() && mop.getReg() && - MRegisterInfo::isVirtualRegister(mop.getReg())) { + TargetRegisterInfo::isVirtualRegister(mop.getReg())) { // replace register with representative register unsigned OrigReg = mop.getReg(); unsigned reg = rep(OrigReg); unsigned SubIdx = RegSubIdxMap[OrigReg]; - if (SubIdx && MRegisterInfo::isPhysicalRegister(reg)) - mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx)); + if (SubIdx && TargetRegisterInfo::isPhysicalRegister(reg)) + mii->getOperand(i).setReg(tri_->getSubReg(reg, SubIdx)); else { mii->getOperand(i).setReg(reg); mii->getOperand(i).setSubReg(SubIdx); @@ -1483,7 +1483,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) { for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) { LiveInterval &LI = I->second; - if (MRegisterInfo::isVirtualRegister(LI.reg)) { + if (TargetRegisterInfo::isVirtualRegister(LI.reg)) { // If the live interval length is essentially zero, i.e. in every live // range the use follows def immediately, it doesn't make sense to spill // it and hope it will be easier to allocate for this li. diff --git a/lib/CodeGen/SimpleRegisterCoalescing.h b/lib/CodeGen/SimpleRegisterCoalescing.h index 575ea57..1120fb3 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.h +++ b/lib/CodeGen/SimpleRegisterCoalescing.h @@ -25,7 +25,7 @@ namespace llvm { class SimpleRegisterCoalescing; class LiveVariables; - class MRegisterInfo; + class TargetRegisterInfo; class TargetInstrInfo; class VirtRegMap; class MachineLoopInfo; @@ -81,7 +81,7 @@ namespace llvm { public RegisterCoalescer { MachineFunction* mf_; const TargetMachine* tm_; - const MRegisterInfo* mri_; + const TargetRegisterInfo* tri_; const TargetInstrInfo* tii_; LiveIntervals *li_; LiveVariables *lv_; diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp index 060f6a6..ce1f6c8 100644 --- a/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -34,7 +34,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Support/Debug.h" @@ -121,8 +121,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) { unsigned regA = mi->getOperand(ti).getReg(); unsigned regB = mi->getOperand(si).getReg(); - assert(MRegisterInfo::isVirtualRegister(regA) && - MRegisterInfo::isVirtualRegister(regB) && + assert(TargetRegisterInfo::isVirtualRegister(regA) && + TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"); #ifndef NDEBUG diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp index 3d2b625..253d5c1 100644 --- a/lib/CodeGen/VirtRegMap.cpp +++ b/lib/CodeGen/VirtRegMap.cpp @@ -79,7 +79,7 @@ void VirtRegMap::grow() { } int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg); @@ -91,7 +91,7 @@ int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) { } void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT && "attempt to assign stack slot to already spilled register"); assert((frameIndex >= 0 || @@ -101,7 +101,7 @@ void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) { } int VirtRegMap::assignVirtReMatId(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && "attempt to assign re-mat id to already spilled register"); Virt2ReMatIdMap[virtReg] = ReMatId; @@ -109,7 +109,7 @@ int VirtRegMap::assignVirtReMatId(unsigned virtReg) { } void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT && "attempt to assign re-mat id to already spilled register"); Virt2ReMatIdMap[virtReg] = id; @@ -135,17 +135,17 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) { } void VirtRegMap::print(std::ostream &OS) const { - const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo(); OS << "********** REGISTER MAP **********\n"; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) { if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG) - OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n"; + OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n"; } - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT) OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n"; @@ -192,7 +192,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); if (MO.isRegister() && MO.getReg()) - if (MRegisterInfo::isVirtualRegister(MO.getReg())) { + if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned VirtReg = MO.getReg(); unsigned PhysReg = VRM.getPhys(VirtReg); if (!VRM.isAssignedReg(VirtReg)) { @@ -242,12 +242,12 @@ namespace { /// register pressure in other blocks). class VISIBILITY_HIDDEN LocalSpiller : public Spiller { MachineRegisterInfo *RegInfo; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; public: bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) { RegInfo = &MF.getRegInfo(); - MRI = MF.getTarget().getRegisterInfo(); + TRI = MF.getTarget().getRegisterInfo(); TII = MF.getTarget().getInstrInfo(); DOUT << "\n**** Local spiller rewriting function '" << MF.getFunction()->getName() << "':\n"; @@ -298,7 +298,7 @@ namespace { /// this bit and addAvailable sets it if. namespace { class VISIBILITY_HIDDEN AvailableSpills { - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled @@ -316,11 +316,11 @@ class VISIBILITY_HIDDEN AvailableSpills { void ClobberPhysRegOnly(unsigned PhysReg); public: - AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii) - : MRI(mri), TII(tii) { + AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii) + : TRI(tri), TII(tii) { } - const MRegisterInfo *getRegInfo() const { return MRI; } + const TargetRegisterInfo *getRegInfo() const { return TRI; } /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is /// available in a physical register, return that PhysReg, otherwise @@ -350,7 +350,7 @@ public: DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1; else DOUT << "Remembering SS#" << SlotOrReMat; - DOUT << " in physreg " << MRI->getName(Reg) << "\n"; + DOUT << " in physreg " << TRI->getName(Reg) << "\n"; } /// canClobberPhysReg - Return true if the spiller is allowed to change the @@ -391,7 +391,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && "Bidirectional map mismatch!"); SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1; - DOUT << "PhysReg " << MRI->getName(PhysReg) + DOUT << "PhysReg " << TRI->getName(PhysReg) << " copied, it is available for use but can no longer be modified\n"; } } @@ -400,7 +400,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) { /// stackslot register and its aliases. The register and its aliases may /// still available but is no longer allowed to be modifed. void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) { - for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) + for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) disallowClobberPhysRegOnly(*AS); disallowClobberPhysRegOnly(PhysReg); } @@ -416,7 +416,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg && "Bidirectional map mismatch!"); SpillSlotsOrReMatsAvailable.erase(SlotOrReMat); - DOUT << "PhysReg " << MRI->getName(PhysReg) + DOUT << "PhysReg " << TRI->getName(PhysReg) << " clobbered, invalidating "; if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT) DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n"; @@ -429,7 +429,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) { /// value. We use this to invalidate any info about stuff we thing lives in /// it and any of its aliases. void AvailableSpills::ClobberPhysReg(unsigned PhysReg) { - for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS) + for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS) ClobberPhysRegOnly(*AS); ClobberPhysRegOnly(PhysReg); } @@ -606,8 +606,8 @@ namespace { std::vector<ReusedOp> Reuses; BitVector PhysRegsClobbered; public: - ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) { - PhysRegsClobbered.resize(mri->getNumRegs()); + ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) { + PhysRegsClobbered.resize(tri->getNumRegs()); } bool hasReuses() const { @@ -670,8 +670,8 @@ namespace { // value aliases the new register. If so, codegen the previous reload // and use this one. unsigned PRRU = Op.PhysRegReused; - const MRegisterInfo *MRI = Spills.getRegInfo(); - if (MRI->areAliases(PRRU, PhysReg)) { + const TargetRegisterInfo *TRI = Spills.getRegInfo(); + if (TRI->areAliases(PRRU, PhysReg)) { // Okay, we found out that an alias of a reused register // was used. This isn't good because it means we have // to undo a previous reuse. @@ -693,7 +693,7 @@ namespace { Rejected, RegKills, KillOps, VRM); if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) { - MRI->reMaterialize(*MBB, MI, NewPhysReg, + TRI->reMaterialize(*MBB, MI, NewPhysReg, VRM.getReMaterializedMI(NewOp.VirtReg)); ++NumReMats; } else { @@ -806,23 +806,23 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, if (!MO.isRegister() || MO.getReg() == 0 || !MO.isUse()) continue; unsigned VirtReg = MO.getReg(); - if (MRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) + if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg()) continue; if (VRM.isAssignedReg(VirtReg)) { unsigned PhysReg = VRM.getPhys(VirtReg); - if (PhysReg && MRI->regsOverlap(PhysReg, UnfoldPR)) + if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR)) return false; } else if (VRM.isReMaterialized(VirtReg)) continue; int SS = VRM.getStackSlot(VirtReg); unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS); if (PhysReg) { - if (MRI->regsOverlap(PhysReg, UnfoldPR)) + if (TRI->regsOverlap(PhysReg, UnfoldPR)) return false; continue; } PhysReg = VRM.getPhys(VirtReg); - if (!MRI->regsOverlap(PhysReg, UnfoldPR)) + if (!TRI->regsOverlap(PhysReg, UnfoldPR)) continue; // Ok, we'll need to reload the value into a register which makes @@ -858,11 +858,11 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB, /// findSuperReg - Find the SubReg's super-register of given register class /// where its SubIdx sub-register is SubReg. static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg, - unsigned SubIdx, const MRegisterInfo *MRI) { + unsigned SubIdx, const TargetRegisterInfo *TRI) { for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; ++I) { unsigned Reg = *I; - if (MRI->getSubReg(Reg, SubIdx) == SubReg) + if (TRI->getSubReg(Reg, SubIdx) == SubReg) return Reg; } return 0; @@ -935,7 +935,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // Spills - Keep track of which spilled values are available in physregs so // that we can choose to reuse the physregs instead of emitting reloads. - AvailableSpills Spills(MRI, TII); + AvailableSpills Spills(TRI, TII); // MaybeDeadStores - When we need to write a value back into a stack slot, // keep track of the inserted store. If the stack slot value is never read @@ -950,9 +950,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { SmallSet<MachineInstr*, 4> ReMatDefs; // Keep track of kill information. - BitVector RegKills(MRI->getNumRegs()); + BitVector RegKills(TRI->getNumRegs()); std::vector<MachineOperand*> KillOps; - KillOps.resize(MRI->getNumRegs(), NULL); + KillOps.resize(TRI->getNumRegs(), NULL); for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); MII != E; ) { @@ -978,7 +978,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { unsigned Phys = VRM.getPhys(VirtReg); RegInfo->setPhysRegUsed(Phys); if (VRM.isReMaterialized(VirtReg)) { - MRI->reMaterialize(MBB, &MI, Phys, + TRI->reMaterialize(MBB, &MI, Phys, VRM.getReMaterializedMI(VirtReg)); ++NumReMats; } else { @@ -1016,7 +1016,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { /// ReusedOperands - Keep track of operand reuse in case we need to undo /// reuse. - ReuseInfo ReusedOperands(MI, MRI); + ReuseInfo ReusedOperands(MI, TRI); // Process all of the spilled uses and all non spilled reg references. for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { MachineOperand &MO = MI.getOperand(i); @@ -1024,14 +1024,14 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { continue; // Ignore non-register operands. unsigned VirtReg = MO.getReg(); - if (MRegisterInfo::isPhysicalRegister(VirtReg)) { + if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) { // Ignore physregs for spilling, but remember that it is used by this // function. RegInfo->setPhysRegUsed(VirtReg); continue; } - assert(MRegisterInfo::isVirtualRegister(VirtReg) && + assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Not a virtual or a physical register?"); unsigned SubIdx = MO.getSubReg(); @@ -1041,7 +1041,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { RegInfo->setPhysRegUsed(Phys); if (MO.isDef()) ReusedOperands.markClobbered(Phys); - unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys; + unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys; MI.getOperand(i).setReg(RReg); continue; } @@ -1100,10 +1100,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { else DOUT << "Reusing SS#" << ReuseSlot; DOUT << " from physreg " - << MRI->getName(PhysReg) << " for vreg" + << TRI->getName(PhysReg) << " for vreg" << VirtReg <<" instead of reloading into physreg " - << MRI->getName(VRM.getPhys(VirtReg)) << "\n"; - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + << TRI->getName(VRM.getPhys(VirtReg)) << "\n"; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); // The only technical detail we have is that we don't know that @@ -1173,10 +1173,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1; else DOUT << "Reusing SS#" << ReuseSlot; - DOUT << " from physreg " << MRI->getName(PhysReg) << " for vreg" + DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg" << VirtReg << " instead of reloading into same physreg.\n"; - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); ReusedOperands.markClobbered(RReg); ++NumReused; @@ -1196,7 +1196,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { Spills.addAvailable(ReuseSlot, &MI, DesignatedReg); unsigned RReg = - SubIdx ? MRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; + SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg; MI.getOperand(i).setReg(RReg); DOUT << '\t' << *prior(MII); ++NumReused; @@ -1218,7 +1218,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { RegInfo->setPhysRegUsed(PhysReg); ReusedOperands.markClobbered(PhysReg); if (DoReMat) { - MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); + TRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg)); ++NumReMats; } else { const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg); @@ -1236,7 +1236,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { // unless it's a two-address operand. if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1) MI.getOperand(i).setIsKill(); - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; MI.getOperand(i).setReg(RReg); UpdateKills(*prior(MII), RegKills, KillOps); DOUT << '\t' << *prior(MII); @@ -1367,7 +1367,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { int StackSlot; if (!(MR & VirtRegMap::isRef)) { if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) { - assert(MRegisterInfo::isPhysicalRegister(SrcReg) && + assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && "Src hasn't been allocated yet?"); // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark // this as a potentially dead store in case there is a subsequent @@ -1390,7 +1390,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { continue; unsigned VirtReg = MO.getReg(); - if (!MRegisterInfo::isVirtualRegister(VirtReg)) { + if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) { // Check to see if this is a noop copy. If so, eliminate the // instruction before considering the dest reg to be changed. unsigned Src, Dst; @@ -1440,8 +1440,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { if (TiedOp != -1) { PhysReg = MI.getOperand(TiedOp).getReg(); if (SubIdx) { - unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI); - assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg && + unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI); + assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg && "Can't find corresponding super-register!"); PhysReg = SuperReg; } @@ -1456,7 +1456,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) { } RegInfo->setPhysRegUsed(PhysReg); - unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg; + unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg; ReusedOperands.markClobbered(RReg); MI.getOperand(i).setReg(RReg); diff --git a/lib/CodeGen/VirtRegMap.h b/lib/CodeGen/VirtRegMap.h index 3b8c362..a7f47de 100644 --- a/lib/CodeGen/VirtRegMap.h +++ b/lib/CodeGen/VirtRegMap.h @@ -17,7 +17,7 @@ #ifndef LLVM_CODEGEN_VIRTREGMAP_H #define LLVM_CODEGEN_VIRTREGMAP_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/IndexedMap.h" #include "llvm/Support/Streams.h" @@ -115,15 +115,15 @@ namespace llvm { /// @brief returns the physical register mapped to the specified /// virtual register unsigned getPhys(unsigned virtReg) const { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); return Virt2PhysMap[virtReg]; } /// @brief creates a mapping for the specified virtual register to /// the specified physical register void assignVirt2Phys(unsigned virtReg, unsigned physReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg) && - MRegisterInfo::isPhysicalRegister(physReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg) && + TargetRegisterInfo::isPhysicalRegister(physReg)); assert(Virt2PhysMap[virtReg] == NO_PHYS_REG && "attempt to assign physical register to already mapped " "virtual register"); @@ -133,7 +133,7 @@ namespace llvm { /// @brief clears the specified virtual register's, physical /// register mapping void clearVirt(unsigned virtReg) { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); assert(Virt2PhysMap[virtReg] != NO_PHYS_REG && "attempt to clear a not assigned virtual register"); Virt2PhysMap[virtReg] = NO_PHYS_REG; @@ -169,14 +169,14 @@ namespace llvm { /// @brief returns the stack slot mapped to the specified virtual /// register int getStackSlot(unsigned virtReg) const { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); return Virt2StackSlotMap[virtReg]; } /// @brief returns the rematerialization id mapped to the specified virtual /// register int getReMatId(unsigned virtReg) const { - assert(MRegisterInfo::isVirtualRegister(virtReg)); + assert(TargetRegisterInfo::isVirtualRegister(virtReg)); return Virt2ReMatIdMap[virtReg]; } diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp index 609b4c4..0d10097 100644 --- a/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/lib/Target/ARM/ARMAsmPrinter.cpp @@ -272,7 +272,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum, const MachineOperand &MO = MI->getOperand(opNum); switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << TM.getRegisterInfo()->get(MO.getReg()).Name; else assert(0 && "not implemented"); @@ -392,7 +392,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << TM.getRegisterInfo()->get(MO1.getReg()).Name; // Print the shift opc. @@ -401,7 +401,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) { << " "; if (MO2.getReg()) { - assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); O << TM.getRegisterInfo()->get(MO2.getReg()).Name; assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); } else { @@ -468,7 +468,7 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) { const MachineOperand &MO2 = MI->getOperand(Op+1); const MachineOperand &MO3 = MI->getOperand(Op+2); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name; if (MO2.getReg()) { @@ -532,7 +532,7 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op, return; } - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); if (Modifier && strcmp(Modifier, "submode") == 0) { ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm()); @@ -569,7 +569,7 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op, } const MachineOperand &MO1 = MI->getOperand(Op); - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]"; } diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 2105f14..62ea102 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -134,7 +134,7 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) { intptr_t rv = 0; const MachineOperand &MO = MI.getOperand(OpIndex); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())); rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); } else if (MO.isImmediate()) { rv = MO.getImm(); @@ -478,7 +478,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) if(IsShiftByRegister) { // set the value of bit[11:8] (register Rs). - assert(MRegisterInfo::isPhysicalRegister(MO1.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg()); assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); Value |= op << ARMII::RegRsShift; @@ -540,7 +540,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { // set bit I(25), because this is not in immediate enconding. Value |= 1 << ARMII::I_BitShift; - assert(MRegisterInfo::isPhysicalRegister(MO2.getReg())); + assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); // set bit[3:0] to the corresponding Rm register Value |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); @@ -640,7 +640,8 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) { for (unsigned i = OpIndex + 4, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MOR = MI.getOperand(i); unsigned RegNumber = ARMRegisterInfo::getRegisterNumbering(MOR.getReg()); - assert(MRegisterInfo::isPhysicalRegister(MOR.getReg()) && RegNumber < 16); + assert(TargetRegisterInfo::isPhysicalRegister(MOR.getReg()) && + RegNumber < 16); Value |= 0x1 << RegNumber; } diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 4d1819d..30c1742 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -282,7 +282,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.getReg() && - MRegisterInfo::isVirtualRegister(MO.getReg())) { + TargetRegisterInfo::isVirtualRegister(MO.getReg())) { unsigned Reg = MO.getReg(); LiveVariables::VarInfo &VI = LV.getVarInfo(Reg); if (MO.isDef()) { diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 31216e4..4ce90fc 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -134,7 +134,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 6c99c3a..5eeeafb 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -26,7 +26,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/Compiler.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" using namespace llvm; @@ -42,7 +42,7 @@ namespace { ARMLoadStoreOpt() : MachineFunctionPass((intptr_t)&ID) {} const TargetInstrInfo *TII; - const MRegisterInfo *MRI; + const TargetRegisterInfo *TRI; ARMFunctionInfo *AFI; RegScavenger *RS; @@ -755,7 +755,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { const TargetMachine &TM = Fn.getTarget(); AFI = Fn.getInfo<ARMFunctionInfo>(); TII = TM.getInstrInfo(); - MRI = TM.getRegisterInfo(); + TRI = TM.getRegisterInfo(); RS = new RegScavenger(); bool Modified = false; diff --git a/lib/Target/ARM/ARMMachineFunctionInfo.h b/lib/Target/ARM/ARMMachineFunctionInfo.h index aa269e3..eeb61d7 100644 --- a/lib/Target/ARM/ARMMachineFunctionInfo.h +++ b/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -16,7 +16,7 @@ #include "ARMSubtarget.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/BitVector.h" diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index b3f6d94..dccc77f 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of the MRegisterInfo class. +// This file contains the ARM implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h index cf18e86..90def1f 100644 --- a/lib/Target/ARM/ARMRegisterInfo.h +++ b/lib/Target/ARM/ARMRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of the MRegisterInfo class. +// This file contains the ARM implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef ARMREGISTERINFO_H #define ARMREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "ARMGenRegisterInfo.h.inc" namespace llvm { diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 233cc24..61c77e6 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -157,7 +157,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, GPRClass::iterator GPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>(); GPRClass::iterator I; if (Subtarget.isThumb()) diff --git a/lib/Target/ARM/ARMTargetMachine.h b/lib/Target/ARM/ARMTargetMachine.h index 4bdfd48..84416d6 100644 --- a/lib/Target/ARM/ARMTargetMachine.h +++ b/lib/Target/ARM/ARMTargetMachine.h @@ -41,7 +41,7 @@ public: virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual TargetJITInfo *getJITInfo() { return &JITInfo; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp index 03ed3d6..067a8ef 100644 --- a/lib/Target/Alpha/AlphaAsmPrinter.cpp +++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp @@ -75,7 +75,8 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); if (MO.getType() == MachineOperand::MO_Register) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImm(); @@ -87,7 +88,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum) void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index d20e1f7..cf646ef 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -261,7 +261,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, VarArgsOffset = (Op.Val->getNumValues()-1) * 8; std::vector<SDOperand> LS; for (int i = 0; i < 6; ++i) { - if (MRegisterInfo::isPhysicalRegister(args_int[i])) + if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); @@ -269,7 +269,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG, SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64); LS.push_back(DAG.getStore(Root, argt, SDFI, NULL, 0)); - if (MRegisterInfo::isPhysicalRegister(args_float[i])) + if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h index 20d6388..0b51f2d 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.h +++ b/lib/Target/Alpha/AlphaInstrInfo.h @@ -28,7 +28,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index d749d35..c9a87dc 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h index 7a32bf5..74037f5 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.h +++ b/lib/Target/Alpha/AlphaRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef ALPHAREGISTERINFO_H #define ALPHAREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "AlphaGenRegisterInfo.h.inc" namespace llvm { diff --git a/lib/Target/Alpha/AlphaTargetMachine.h b/lib/Target/Alpha/AlphaTargetMachine.h index 0399d1a..5c74181 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.h +++ b/lib/Target/Alpha/AlphaTargetMachine.h @@ -43,7 +43,7 @@ public: virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual TargetLowering* getTargetLowering() const { diff --git a/lib/Target/CellSPU/SPUAsmPrinter.cpp b/lib/Target/CellSPU/SPUAsmPrinter.cpp index e5e7d04..b62bf62 100644 --- a/lib/Target/CellSPU/SPUAsmPrinter.cpp +++ b/lib/Target/CellSPU/SPUAsmPrinter.cpp @@ -31,7 +31,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" @@ -73,14 +73,15 @@ namespace { /// void printRegister(const MachineOperand &MO, bool R0AsZero) { unsigned RegNo = MO.getReg(); - assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && + "Not physreg??"); O << TM.getRegisterInfo()->get(RegNo).Name; } void printOperand(const MachineInstr *MI, unsigned OpNo) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImm(); diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index 39237ee..c5fe811 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -30,7 +30,7 @@ namespace llvm { /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp index 39edccb..4a60755 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.cpp +++ b/lib/Target/CellSPU/SPURegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Cell implementation of the MRegisterInfo class. +// This file contains the Cell implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/CellSPU/SPURegisterInfo.h b/lib/Target/CellSPU/SPURegisterInfo.h index aa2f036..f54c111 100644 --- a/lib/Target/CellSPU/SPURegisterInfo.h +++ b/lib/Target/CellSPU/SPURegisterInfo.h @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Cell SPU implementation of the MRegisterInfo class. +// This file contains the Cell SPU implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/CellSPU/SPUTargetMachine.h b/lib/Target/CellSPU/SPUTargetMachine.h index 8d05ab9..6f1cabb 100644 --- a/lib/Target/CellSPU/SPUTargetMachine.h +++ b/lib/Target/CellSPU/SPUTargetMachine.h @@ -70,7 +70,7 @@ public: return const_cast<SPUTargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp index c6d6626..4efc672 100644 --- a/lib/Target/IA64/IA64AsmPrinter.cpp +++ b/lib/Target/IA64/IA64AsmPrinter.cpp @@ -53,7 +53,8 @@ namespace { void printOperand(const MachineInstr *MI, unsigned OpNo){ const MachineOperand &MO = MI->getOperand(OpNo); if (MO.getType() == MachineOperand::MO_Register) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physref??"); //XXX Bug Workaround: See note in Printer::doInitialization about %. O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { @@ -164,7 +165,7 @@ bool IA64AsmPrinter::runOnMachineFunction(MachineFunction &MF) { void IA64AsmPrinter::printOp(const MachineOperand &MO, bool isBRCALLinsn /* = false */) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: O << RI.get(MO.getReg()).Name; diff --git a/lib/Target/IA64/IA64InstrInfo.h b/lib/Target/IA64/IA64InstrInfo.h index 0508973..e5da6f1 100644 --- a/lib/Target/IA64/IA64InstrInfo.h +++ b/lib/Target/IA64/IA64InstrInfo.h @@ -28,7 +28,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } // // Return true if the instruction is a register to register move and diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index dae53d0..2204873 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the IA64 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on IA64. +// This file contains the IA64 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on IA64. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h index 6e682e3..510f771 100644 --- a/lib/Target/IA64/IA64RegisterInfo.h +++ b/lib/Target/IA64/IA64RegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the IA64 implementation of the MRegisterInfo class. +// This file contains the IA64 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef IA64REGISTERINFO_H #define IA64REGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "IA64GenRegisterInfo.h.inc" namespace llvm { class llvm::Type; } diff --git a/lib/Target/IA64/IA64TargetMachine.h b/lib/Target/IA64/IA64TargetMachine.h index 2831ea9..5b320c2 100644 --- a/lib/Target/IA64/IA64TargetMachine.h +++ b/lib/Target/IA64/IA64TargetMachine.h @@ -40,7 +40,7 @@ public: virtual IA64TargetLowering *getTargetLowering() const { return const_cast<IA64TargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 28cbdea..872e51c 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -162,7 +162,7 @@ emitFMaskDirective(MachineFunction &MF) void MipsAsmPrinter:: emitFrameDirective(MachineFunction &MF) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned stackReg = RI.getFrameRegister(MF); unsigned returnReg = RI.getRARegister(); @@ -195,7 +195,7 @@ emitSetDirective(SetDirectiveFlags Flag) unsigned int MipsAsmPrinter:: getSavedRegsBitmask(bool isFloat, MachineFunction &MF) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); // Float Point Registers, TODO if (isFloat) @@ -323,7 +323,7 @@ void MipsAsmPrinter:: printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand(opNum); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); bool closeP = false; bool isPIC = (TM.getRelocationModel() == Reloc::PIC_); bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large); @@ -364,7 +364,7 @@ printOperand(const MachineInstr *MI, int opNum) switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << "$" << LowercaseString (RI.get(MO.getReg()).Name); else O << "$" << MO.getReg(); diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index d894b20..a186f2c 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -52,7 +52,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index e4dabc0..4ca5ade 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the MIPS implementation of the MRegisterInfo class. +// This file contains the MIPS implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index 2181cdf..e491a95 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Mips implementation of the MRegisterInfo class. +// This file contains the Mips implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef MIPSREGISTERINFO_H #define MIPSREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "MipsGenRegisterInfo.h.inc" namespace llvm { diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index 859387e..d974d3c 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -44,7 +44,7 @@ namespace llvm { virtual const TargetData *getTargetData() const { return &DataLayout;} - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 95825bb..71ce147 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -37,7 +37,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/Compiler.h" #include "llvm/Target/TargetAsmInfo.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/Statistic.h" @@ -105,7 +105,7 @@ namespace { /// void printRegister(const MachineOperand &MO, bool R0AsZero) { unsigned RegNo = MO.getReg(); - assert(MRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); // If we should use 0 for R0. if (R0AsZero && RegNo == PPC::R0) { diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 09fef25..f4aaaad 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -225,7 +225,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { // by the scheduler. Detect them now. MachineFunction &Fn = MachineFunction::get(&F); bool HasVectorVReg = false; - for (unsigned i = MRegisterInfo::FirstVirtualRegister, + for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, e = RegInfo->getLastVirtReg()+1; i != e; ++i) if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { HasVectorVReg = true; diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index 9f289e4..5836d1f 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -71,7 +71,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// getPointerRegClass - Return the register class to use to hold pointers. /// This is used for addressing modes. diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index efed072..a21abe5 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PowerPC implementation of the MRegisterInfo class. +// This file contains the PowerPC implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index 2a84fc2..fc17b02 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -7,7 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PowerPC implementation of the MRegisterInfo class. +// This file contains the PowerPC implementation of the TargetRegisterInfo +// class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 769e137..1d76d15 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -51,7 +51,7 @@ public: virtual PPCTargetLowering *getTargetLowering() const { return const_cast<PPCTargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 12eae8a..b95acdd 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -132,7 +132,7 @@ bool SparcAsmPrinter::runOnMachineFunction(MachineFunction &MF) { void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { const MachineOperand &MO = MI->getOperand (opNum); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); bool CloseParen = false; if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) { O << "%hi("; @@ -144,7 +144,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) { } switch (MO.getType()) { case MachineOperand::MO_Register: - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) O << "%" << LowercaseString (RI.get(MO.getReg()).Name); else O << "%reg" << MO.getReg(); diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 14c3b4a..22b2dcd 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -41,7 +41,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } /// Return true if the instruction is a register to register move and /// leave the source and dest operands in the passed parameters. diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 6b93c68..cd50ad1 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the SPARC implementation of the MRegisterInfo class. +// This file contains the SPARC implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 2235de1..fe2c8ee 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -7,14 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Sparc implementation of the MRegisterInfo class. +// This file contains the Sparc implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef SPARCREGISTERINFO_H #define SPARCREGISTERINFO_H -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "SparcGenRegisterInfo.h.inc" namespace llvm { diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 61588e8d..0da9293 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -39,7 +39,7 @@ public: virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index 8c022cf..11f1b3d 100644 --- a/lib/Target/MRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- MRegisterInfo.cpp - Target Register Information Implementation -----===// +//===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// // // The LLVM Compiler Infrastructure // @@ -7,12 +7,12 @@ // //===----------------------------------------------------------------------===// // -// This file implements the MRegisterInfo interface. +// This file implements the TargetRegisterInfo interface. // //===----------------------------------------------------------------------===// #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -20,7 +20,7 @@ using namespace llvm; -MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, +TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, regclass_iterator RCB, regclass_iterator RCE, int CFSO, int CFDO) : Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) { @@ -31,12 +31,12 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR, CallFrameDestroyOpcode = CFDO; } -MRegisterInfo::~MRegisterInfo() {} +TargetRegisterInfo::~TargetRegisterInfo() {} /// getPhysicalRegisterRegClass - Returns the Register Class of a physical /// register. const TargetRegisterClass * -MRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, +TargetRegisterInfo::getPhysicalRegisterRegClass(MVT::ValueType VT, unsigned reg) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the register class of the right type that contains this physreg. @@ -57,15 +57,15 @@ static void getAllocatableSetForRC(MachineFunction &MF, R.set(*I); } -BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, - const TargetRegisterClass *RC) const { +BitVector TargetRegisterInfo::getAllocatableSet(MachineFunction &MF, + const TargetRegisterClass *RC) const { BitVector Allocatable(NumRegs); if (RC) { getAllocatableSetForRC(MF, RC, Allocatable); return Allocatable; } - for (MRegisterInfo::regclass_iterator I = regclass_begin(), + for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) getAllocatableSetForRC(MF, *I, Allocatable); return Allocatable; @@ -74,7 +74,7 @@ BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF, /// getFrameIndexOffset - Returns the displacement from the frame register to /// the stack frame of the specified index. This is the default implementation /// which is likely incorrect for the target. -int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { +int TargetRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->getObjectOffset(FI) + MFI->getStackSize() - @@ -84,7 +84,7 @@ int MRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to a function. void -MRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const { +TargetRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const { // Default is to do nothing. } diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp index a5b1b79..d315bb4 100644 --- a/lib/Target/X86/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/X86ATTAsmPrinter.cpp @@ -216,10 +216,10 @@ static inline bool printStub(TargetMachine &TM, const X86Subtarget* ST) { void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, const char *Modifier, bool NotRIPRel) { const MachineOperand &MO = MI->getOperand(OpNo); - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Virtual registers should not make it this far!"); O << '%'; unsigned Reg = MO.getReg(); @@ -553,7 +553,7 @@ void X86ATTAsmPrinter::printPICJumpTableEntry(const MachineJumpTableInfo *MJTI, bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, const char Mode) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 0703563..53de9d8 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -569,7 +569,7 @@ void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { const TargetRegisterClass *clas; for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) { if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() && - MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && + TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) && ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) == X86::RFP32RegisterClass || clas == X86::RFP64RegisterClass || diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index e445470..f131c57 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1051,7 +1051,7 @@ static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op) { if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS || (Op.getOpcode()== ISD::CopyFromReg && (OpReg = cast<RegisterSDNode>(Op.getOperand(1))) && - OpReg->getReg() >= MRegisterInfo::FirstVirtualRegister)) + OpReg->getReg() >= TargetRegisterInfo::FirstVirtualRegister)) return true; return false; } diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 6bf76af..b14e3dc 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -445,7 +445,7 @@ namespace llvm { /// Subtarget - Keep a pointer to the X86Subtarget around so that we can /// make the right decision when generating code for different targets. const X86Subtarget *Subtarget; - const MRegisterInfo *RegInfo; + const TargetRegisterInfo *RegInfo; /// X86StackPtr - X86 physical register used as stack ptr. unsigned X86StackPtr; diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 4a62e9e..7a1ab51 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -17,7 +17,7 @@ #include "llvm/Target/TargetInstrInfo.h" #include "X86RegisterInfo.h" #include "llvm/ADT/IndexedMap.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { class X86RegisterInfo; @@ -245,7 +245,7 @@ public: /// such, whenever a client has an instance of instruction info, it should /// always be able to get register info as well (through this method). /// - virtual const MRegisterInfo &getRegisterInfo() const { return RI; } + virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; } // Return true if the instruction is a register to register move and // leave the source and dest operands in the passed parameters. diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp index 029533e..804790d 100644 --- a/lib/Target/X86/X86IntelAsmPrinter.cpp +++ b/lib/Target/X86/X86IntelAsmPrinter.cpp @@ -114,10 +114,10 @@ void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) { void X86IntelAsmPrinter::printOp(const MachineOperand &MO, const char *Modifier) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); switch (MO.getType()) { case MachineOperand::MO_Register: { - if (MRegisterInfo::isPhysicalRegister(MO.getReg())) { + if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { MVT::ValueType VT = (strcmp(Modifier,"subreg64") == 0) ? @@ -252,7 +252,7 @@ void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) { bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO, const char Mode) { - const MRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getRegisterInfo(); unsigned Reg = MO.getReg(); switch (Mode) { default: return true; // Unknown mode. diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h index f8dd6bc..8e7a31c 100644 --- a/lib/Target/X86/X86IntelAsmPrinter.h +++ b/lib/Target/X86/X86IntelAsmPrinter.h @@ -16,7 +16,7 @@ #include "X86AsmPrinter.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { @@ -41,7 +41,8 @@ struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public X86SharedAsmPrinter { const char *Modifier = 0) { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.isRegister()) { - assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??"); + assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && + "Not physreg??"); O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else { printOp(MO, Modifier); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 931df4d..10a0eec 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on X86. +// This file contains the X86 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on X86. // //===----------------------------------------------------------------------===// diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 02f237d..8b010a9 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -7,7 +7,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. +// This file contains the X86 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// @@ -16,7 +16,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallVector.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "X86GenRegisterInfo.h.inc" namespace llvm { diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 42c7ce7..9d70618 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -249,7 +249,7 @@ def GR8 : RegisterClass<"X86", [i8], 8, GR8Class::iterator GR8Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (!Subtarget.is64Bit()) return X86_GR8_AO_32; @@ -262,7 +262,7 @@ def GR8 : RegisterClass<"X86", [i8], 8, GR8Class::iterator GR8Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (!Subtarget.is64Bit()) return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned)); @@ -303,7 +303,7 @@ def GR16 : RegisterClass<"X86", [i16], 16, GR16Class::iterator GR16Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -321,7 +321,7 @@ def GR16 : RegisterClass<"X86", [i16], 16, GR16Class::iterator GR16Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -367,7 +367,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -385,7 +385,7 @@ def GR32 : RegisterClass<"X86", [i32], 32, GR32Class::iterator GR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>(); if (Subtarget.is64Bit()) { if (RI->hasFP(MF)) @@ -414,7 +414,7 @@ def GR64 : RegisterClass<"X86", [i64], 64, GR64Class::iterator GR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const MRegisterInfo *RI = TM.getRegisterInfo(); + const TargetRegisterInfo *RI = TM.getRegisterInfo(); if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr? return end()-2; // If so, don't allocate RSP or RBP else diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 58c9697..e9148b5 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -49,7 +49,7 @@ public: virtual X86TargetLowering *getTargetLowering() const { return const_cast<X86TargetLowering*>(&TLInfo); } - virtual const MRegisterInfo *getRegisterInfo() const { + virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } virtual const TargetData *getTargetData() const { return &DataLayout; } |