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authorEvan Cheng <evan.cheng@apple.com>2007-09-14 01:57:02 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-09-14 01:57:02 +0000
commit7567ba12d47125a2a552a17e6c6a6fd5ca83ee74 (patch)
treeb36f3d4e247e96e2ac3a108fc0936eb66b6bf28d /lib
parentd08ddaed42a309078b42828b7477125f14c4057f (diff)
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Fix comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index cd50413..2f1990e 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -157,8 +157,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addReg(PPC::R0, false, false, true), FrameIdx);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
- // R11 = ADDI FI#
- // Dest = LVX R0, R11
+ // R0 = ADDI FI#
+ // STVX VAL, 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
@@ -210,8 +210,8 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
- // R11 = ADDI FI#
- // Dest = LVX R0, R11
+ // R0 = ADDI FI#
+ // Dest = LVX 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),