Add some simplifications for demanded bits, this allows instcombine to turn:

define i64 @test(i64 %A, i32 %B) {
        %tmp12 = zext i32 %B to i64             ; <i64> [#uses=1]
        %tmp3 = shl i64 %tmp12, 32              ; <i64> [#uses=1]
        %tmp5 = add i64 %tmp3, %A               ; <i64> [#uses=1]
        %tmp6 = and i64 %tmp5, 123              ; <i64> [#uses=1]
        ret i64 %tmp6
}

into:

define i64 @test(i64 %A, i32 %B) {
        %tmp6 = and i64 %A, 123         ; <i64> [#uses=1]
        ret i64 %tmp6
}

This implements Transforms/InstCombine/add2.ll:test1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34919 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 31 insertions, 0 deletions

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index e8dbb73..028fa73 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -1186,6 +1186,37 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, uint64_t DemandedMask,
       // Bits are known zero if they are known zero in both operands and there
       // is no input carry.
       KnownZero = KnownZero2 & ~RHSVal & ~CarryBits;
+    } else {
+      // If the high-bits of this ADD are not demanded, then it does not demand
+      // the high bits of its LHS or RHS.
+      if ((DemandedMask & VTy->getSignBit()) == 0) {
+        // Right fill the mask of bits for this ADD to demand the most
+        // significant bit and all those below it.
+        unsigned NLZ = CountLeadingZeros_64(DemandedMask);
+        uint64_t DemandedFromOps = ~0ULL >> NLZ;
+        if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps,
+                                 KnownZero2, KnownOne2, Depth+1))
+          return true;
+        if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps,
+                                 KnownZero2, KnownOne2, Depth+1))
+          return true;
+      }
+    }
+    break;
+  case Instruction::Sub:
+    // If the high-bits of this SUB are not demanded, then it does not demand
+    // the high bits of its LHS or RHS.
+    if ((DemandedMask & VTy->getSignBit()) == 0) {
+      // Right fill the mask of bits for this SUB to demand the most
+      // significant bit and all those below it.
+      unsigned NLZ = CountLeadingZeros_64(DemandedMask);
+      uint64_t DemandedFromOps = ~0ULL >> NLZ;
+      if (SimplifyDemandedBits(I->getOperand(0), DemandedFromOps,
+                               KnownZero2, KnownOne2, Depth+1))
+        return true;
+      if (SimplifyDemandedBits(I->getOperand(1), DemandedFromOps,
+                               KnownZero2, KnownOne2, Depth+1))
+        return true;
     }
     break;
   case Instruction::Shl: