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authorEvan Cheng <evan.cheng@apple.com>2012-01-08 20:41:16 +0000
committerEvan Cheng <evan.cheng@apple.com>2012-01-08 20:41:16 +0000
commit79aa048d2102a7d4c8abbba82b4b8a41dbc32214 (patch)
treead4f0d8b80ffa48b0c2f94ba603cacd52d1e31b7 /lib
parente811d0dd30e8949df5d72bedfaa46dc579dad97e (diff)
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Don't forget to transfer implicit uses of return instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147752 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/Thumb1FrameLowering.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/ARM/Thumb1FrameLowering.cpp b/lib/Target/ARM/Thumb1FrameLowering.cpp
index 16c7cbc..bb327b0 100644
--- a/lib/Target/ARM/Thumb1FrameLowering.cpp
+++ b/lib/Target/ARM/Thumb1FrameLowering.cpp
@@ -278,8 +278,11 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF,
emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize);
- AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
- .addReg(ARM::R3, RegState::Kill));
+ MachineInstrBuilder MIB =
+ BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg))
+ .addReg(ARM::R3, RegState::Kill);
+ AddDefaultPred(MIB);
+ MIB->copyImplicitOps(&*MBBI);
// erase the old tBX_RET instruction
MBB.erase(MBBI);
}