Silence various build warnings from Hexagon backend that show up in release builds. Mostly converting 'assert(0)' to 'llvm_unreachable' to silence warnings about missing returns. Also fold some variable declarations into asserts to prevent the variables from being unused in release builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154660 91177308-0d34-0410-b5e6-96231b3b80d8

5 files changed, 220 insertions, 240 deletions

diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 06e57ec..2cc8b81 100644
--- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -78,8 +78,7 @@ void HexagonAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
   const MachineOperand &MO = MI->getOperand(OpNo);
 
   switch (MO.getType()) {
-  default:
-    assert(0 && "<unknown operand type>");
+  default: llvm_unreachable("<unknown operand type>");
   case MachineOperand::MO_Register:
     O << HexagonInstPrinter::getRegisterName(MO.getReg());
     return;
diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 6d3267e..8685ec1 100644
--- a/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -846,105 +846,107 @@ bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
 
 unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
   switch(MI->getOpcode()) {
-    // JMP_EQri
-    case Hexagon::JMP_EQriPt_nv_V4:
-      return Hexagon::JMP_EQriPt_ie_nv_V4;
-    case Hexagon::JMP_EQriNotPt_nv_V4:
-      return Hexagon::JMP_EQriNotPt_ie_nv_V4;
-    case Hexagon::JMP_EQriPnt_nv_V4:
-      return Hexagon::JMP_EQriPnt_ie_nv_V4;
-    case Hexagon::JMP_EQriNotPnt_nv_V4:
-      return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
-
-    // JMP_EQri -- with -1
-    case Hexagon::JMP_EQriPtneg_nv_V4:
-      return Hexagon::JMP_EQriPtneg_ie_nv_V4;
-    case Hexagon::JMP_EQriNotPtneg_nv_V4:
-      return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
-    case Hexagon::JMP_EQriPntneg_nv_V4:
-      return Hexagon::JMP_EQriPntneg_ie_nv_V4;
-    case Hexagon::JMP_EQriNotPntneg_nv_V4:
-      return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
-
-    // JMP_EQrr
-    case Hexagon::JMP_EQrrPt_nv_V4:
-      return Hexagon::JMP_EQrrPt_ie_nv_V4;
-    case Hexagon::JMP_EQrrNotPt_nv_V4:
-      return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
-    case Hexagon::JMP_EQrrPnt_nv_V4:
-      return Hexagon::JMP_EQrrPnt_ie_nv_V4;
-    case Hexagon::JMP_EQrrNotPnt_nv_V4:
-      return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
-
-    // JMP_GTri
-    case Hexagon::JMP_GTriPt_nv_V4:
-      return Hexagon::JMP_GTriPt_ie_nv_V4;
-    case Hexagon::JMP_GTriNotPt_nv_V4:
-      return Hexagon::JMP_GTriNotPt_ie_nv_V4;
-    case Hexagon::JMP_GTriPnt_nv_V4:
-      return Hexagon::JMP_GTriPnt_ie_nv_V4;
-    case Hexagon::JMP_GTriNotPnt_nv_V4:
-      return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
-
-    // JMP_GTri -- with -1
-    case Hexagon::JMP_GTriPtneg_nv_V4:
-      return Hexagon::JMP_GTriPtneg_ie_nv_V4;
-    case Hexagon::JMP_GTriNotPtneg_nv_V4:
-      return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
-    case Hexagon::JMP_GTriPntneg_nv_V4:
-      return Hexagon::JMP_GTriPntneg_ie_nv_V4;
-    case Hexagon::JMP_GTriNotPntneg_nv_V4:
-      return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
-
-    // JMP_GTrr
-    case Hexagon::JMP_GTrrPt_nv_V4:
-      return Hexagon::JMP_GTrrPt_ie_nv_V4;
-    case Hexagon::JMP_GTrrNotPt_nv_V4:
-      return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
-    case Hexagon::JMP_GTrrPnt_nv_V4:
-      return Hexagon::JMP_GTrrPnt_ie_nv_V4;
-    case Hexagon::JMP_GTrrNotPnt_nv_V4:
-      return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
-
-    // JMP_GTrrdn
-    case Hexagon::JMP_GTrrdnPt_nv_V4:
-      return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
-    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
-      return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
-    case Hexagon::JMP_GTrrdnPnt_nv_V4:
-      return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
-    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
-      return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
-
-    // JMP_GTUri
-    case Hexagon::JMP_GTUriPt_nv_V4:
-      return Hexagon::JMP_GTUriPt_ie_nv_V4;
-    case Hexagon::JMP_GTUriNotPt_nv_V4:
-      return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
-    case Hexagon::JMP_GTUriPnt_nv_V4:
-      return Hexagon::JMP_GTUriPnt_ie_nv_V4;
-    case Hexagon::JMP_GTUriNotPnt_nv_V4:
-      return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
-
-    // JMP_GTUrr
-    case Hexagon::JMP_GTUrrPt_nv_V4:
-      return Hexagon::JMP_GTUrrPt_ie_nv_V4;
-    case Hexagon::JMP_GTUrrNotPt_nv_V4:
-      return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
-    case Hexagon::JMP_GTUrrPnt_nv_V4:
-      return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
-    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
-      return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
-
-    // JMP_GTUrrdn
-    case Hexagon::JMP_GTUrrdnPt_nv_V4:
-      return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
-    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
-      return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
-    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
-      return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
-    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
-      return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
+  default: llvm_unreachable("Unknown type of instruction");
+
+  // JMP_EQri
+  case Hexagon::JMP_EQriPt_nv_V4:
+    return Hexagon::JMP_EQriPt_ie_nv_V4;
+  case Hexagon::JMP_EQriNotPt_nv_V4:
+    return Hexagon::JMP_EQriNotPt_ie_nv_V4;
+  case Hexagon::JMP_EQriPnt_nv_V4:
+    return Hexagon::JMP_EQriPnt_ie_nv_V4;
+  case Hexagon::JMP_EQriNotPnt_nv_V4:
+    return Hexagon::JMP_EQriNotPnt_ie_nv_V4;
+
+  // JMP_EQri -- with -1
+  case Hexagon::JMP_EQriPtneg_nv_V4:
+    return Hexagon::JMP_EQriPtneg_ie_nv_V4;
+  case Hexagon::JMP_EQriNotPtneg_nv_V4:
+    return Hexagon::JMP_EQriNotPtneg_ie_nv_V4;
+  case Hexagon::JMP_EQriPntneg_nv_V4:
+    return Hexagon::JMP_EQriPntneg_ie_nv_V4;
+  case Hexagon::JMP_EQriNotPntneg_nv_V4:
+    return Hexagon::JMP_EQriNotPntneg_ie_nv_V4;
+
+  // JMP_EQrr
+  case Hexagon::JMP_EQrrPt_nv_V4:
+    return Hexagon::JMP_EQrrPt_ie_nv_V4;
+  case Hexagon::JMP_EQrrNotPt_nv_V4:
+    return Hexagon::JMP_EQrrNotPt_ie_nv_V4;
+  case Hexagon::JMP_EQrrPnt_nv_V4:
+    return Hexagon::JMP_EQrrPnt_ie_nv_V4;
+  case Hexagon::JMP_EQrrNotPnt_nv_V4:
+    return Hexagon::JMP_EQrrNotPnt_ie_nv_V4;
+
+  // JMP_GTri
+  case Hexagon::JMP_GTriPt_nv_V4:
+    return Hexagon::JMP_GTriPt_ie_nv_V4;
+  case Hexagon::JMP_GTriNotPt_nv_V4:
+    return Hexagon::JMP_GTriNotPt_ie_nv_V4;
+  case Hexagon::JMP_GTriPnt_nv_V4:
+    return Hexagon::JMP_GTriPnt_ie_nv_V4;
+  case Hexagon::JMP_GTriNotPnt_nv_V4:
+    return Hexagon::JMP_GTriNotPnt_ie_nv_V4;
+
+  // JMP_GTri -- with -1
+  case Hexagon::JMP_GTriPtneg_nv_V4:
+    return Hexagon::JMP_GTriPtneg_ie_nv_V4;
+  case Hexagon::JMP_GTriNotPtneg_nv_V4:
+    return Hexagon::JMP_GTriNotPtneg_ie_nv_V4;
+  case Hexagon::JMP_GTriPntneg_nv_V4:
+    return Hexagon::JMP_GTriPntneg_ie_nv_V4;
+  case Hexagon::JMP_GTriNotPntneg_nv_V4:
+    return Hexagon::JMP_GTriNotPntneg_ie_nv_V4;
+
+  // JMP_GTrr
+  case Hexagon::JMP_GTrrPt_nv_V4:
+    return Hexagon::JMP_GTrrPt_ie_nv_V4;
+  case Hexagon::JMP_GTrrNotPt_nv_V4:
+    return Hexagon::JMP_GTrrNotPt_ie_nv_V4;
+  case Hexagon::JMP_GTrrPnt_nv_V4:
+    return Hexagon::JMP_GTrrPnt_ie_nv_V4;
+  case Hexagon::JMP_GTrrNotPnt_nv_V4:
+    return Hexagon::JMP_GTrrNotPnt_ie_nv_V4;
+
+  // JMP_GTrrdn
+  case Hexagon::JMP_GTrrdnPt_nv_V4:
+    return Hexagon::JMP_GTrrdnPt_ie_nv_V4;
+  case Hexagon::JMP_GTrrdnNotPt_nv_V4:
+    return Hexagon::JMP_GTrrdnNotPt_ie_nv_V4;
+  case Hexagon::JMP_GTrrdnPnt_nv_V4:
+    return Hexagon::JMP_GTrrdnPnt_ie_nv_V4;
+  case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
+    return Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4;
+
+  // JMP_GTUri
+  case Hexagon::JMP_GTUriPt_nv_V4:
+    return Hexagon::JMP_GTUriPt_ie_nv_V4;
+  case Hexagon::JMP_GTUriNotPt_nv_V4:
+    return Hexagon::JMP_GTUriNotPt_ie_nv_V4;
+  case Hexagon::JMP_GTUriPnt_nv_V4:
+    return Hexagon::JMP_GTUriPnt_ie_nv_V4;
+  case Hexagon::JMP_GTUriNotPnt_nv_V4:
+    return Hexagon::JMP_GTUriNotPnt_ie_nv_V4;
+
+  // JMP_GTUrr
+  case Hexagon::JMP_GTUrrPt_nv_V4:
+    return Hexagon::JMP_GTUrrPt_ie_nv_V4;
+  case Hexagon::JMP_GTUrrNotPt_nv_V4:
+    return Hexagon::JMP_GTUrrNotPt_ie_nv_V4;
+  case Hexagon::JMP_GTUrrPnt_nv_V4:
+    return Hexagon::JMP_GTUrrPnt_ie_nv_V4;
+  case Hexagon::JMP_GTUrrNotPnt_nv_V4:
+    return Hexagon::JMP_GTUrrNotPnt_ie_nv_V4;
+
+  // JMP_GTUrrdn
+  case Hexagon::JMP_GTUrrdnPt_nv_V4:
+    return Hexagon::JMP_GTUrrdnPt_ie_nv_V4;
+  case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
+    return Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4;
+  case Hexagon::JMP_GTUrrdnPnt_nv_V4:
+    return Hexagon::JMP_GTUrrdnPnt_ie_nv_V4;
+  case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
+    return Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4;
 
   case Hexagon::TFR_FI:
       return Hexagon::TFR_FI_immext_V4;
@@ -991,120 +993,114 @@ unsigned HexagonInstrInfo::getImmExtForm(const MachineInstr* MI) const {
   case Hexagon::MEMb_SUBr_MEM_V4 :
   case Hexagon::MEMb_ANDr_MEM_V4 :
   case Hexagon::MEMb_ORr_MEM_V4 :
-    assert(0 && "Needs implementing");
-
-  default:
-    assert(0 && "Unknown type of instruction");
+    llvm_unreachable("Needs implementing");
   }
-  assert(0 && "Unknown type of instruction");
 }
 
 unsigned HexagonInstrInfo::getNormalBranchForm(const MachineInstr* MI) const {
   switch(MI->getOpcode()) {
-    // JMP_EQri
-    case Hexagon::JMP_EQriPt_ie_nv_V4:
-      return Hexagon::JMP_EQriPt_nv_V4;
-    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
-      return Hexagon::JMP_EQriNotPt_nv_V4;
-    case Hexagon::JMP_EQriPnt_ie_nv_V4:
-      return Hexagon::JMP_EQriPnt_nv_V4;
-    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
-      return Hexagon::JMP_EQriNotPnt_nv_V4;
-
-    // JMP_EQri -- with -1
-    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
-      return Hexagon::JMP_EQriPtneg_nv_V4;
-    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
-      return Hexagon::JMP_EQriNotPtneg_nv_V4;
-    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
-      return Hexagon::JMP_EQriPntneg_nv_V4;
-    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
-      return Hexagon::JMP_EQriNotPntneg_nv_V4;
-
-    // JMP_EQrr
-    case Hexagon::JMP_EQrrPt_ie_nv_V4:
-      return Hexagon::JMP_EQrrPt_nv_V4;
-    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
-      return Hexagon::JMP_EQrrNotPt_nv_V4;
-    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
-      return Hexagon::JMP_EQrrPnt_nv_V4;
-    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
-      return Hexagon::JMP_EQrrNotPnt_nv_V4;
-
-    // JMP_GTri
-    case Hexagon::JMP_GTriPt_ie_nv_V4:
-      return Hexagon::JMP_GTriPt_nv_V4;
-    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
-      return Hexagon::JMP_GTriNotPt_nv_V4;
-    case Hexagon::JMP_GTriPnt_ie_nv_V4:
-      return Hexagon::JMP_GTriPnt_nv_V4;
-    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
-      return Hexagon::JMP_GTriNotPnt_nv_V4;
-
-    // JMP_GTri -- with -1
-    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
-      return Hexagon::JMP_GTriPtneg_nv_V4;
-    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
-      return Hexagon::JMP_GTriNotPtneg_nv_V4;
-    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
-      return Hexagon::JMP_GTriPntneg_nv_V4;
-    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
-      return Hexagon::JMP_GTriNotPntneg_nv_V4;
-
-    // JMP_GTrr
-    case Hexagon::JMP_GTrrPt_ie_nv_V4:
-      return Hexagon::JMP_GTrrPt_nv_V4;
-    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
-      return Hexagon::JMP_GTrrNotPt_nv_V4;
-    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
-      return Hexagon::JMP_GTrrPnt_nv_V4;
-    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
-      return Hexagon::JMP_GTrrNotPnt_nv_V4;
-
-    // JMP_GTrrdn
-    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
-      return Hexagon::JMP_GTrrdnPt_nv_V4;
-    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
-      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
-    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
-      return Hexagon::JMP_GTrrdnPnt_nv_V4;
-    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
-      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
-
-    // JMP_GTUri
-    case Hexagon::JMP_GTUriPt_ie_nv_V4:
-      return Hexagon::JMP_GTUriPt_nv_V4;
-    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
-      return Hexagon::JMP_GTUriNotPt_nv_V4;
-    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
-      return Hexagon::JMP_GTUriPnt_nv_V4;
-    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
-      return Hexagon::JMP_GTUriNotPnt_nv_V4;
-
-    // JMP_GTUrr
-    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrPt_nv_V4;
-    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrNotPt_nv_V4;
-    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrPnt_nv_V4;
-    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
-
-    // JMP_GTUrrdn
-    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrdnPt_nv_V4;
-    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
-    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
-    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
-      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
-
-    default:
-      assert(0 && "Unknown type of jump instruction");
+  default: llvm_unreachable("Unknown type of jump instruction");
+
+  // JMP_EQri
+  case Hexagon::JMP_EQriPt_ie_nv_V4:
+    return Hexagon::JMP_EQriPt_nv_V4;
+  case Hexagon::JMP_EQriNotPt_ie_nv_V4:
+    return Hexagon::JMP_EQriNotPt_nv_V4;
+  case Hexagon::JMP_EQriPnt_ie_nv_V4:
+    return Hexagon::JMP_EQriPnt_nv_V4;
+  case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
+    return Hexagon::JMP_EQriNotPnt_nv_V4;
+
+  // JMP_EQri -- with -1
+  case Hexagon::JMP_EQriPtneg_ie_nv_V4:
+    return Hexagon::JMP_EQriPtneg_nv_V4;
+  case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
+    return Hexagon::JMP_EQriNotPtneg_nv_V4;
+  case Hexagon::JMP_EQriPntneg_ie_nv_V4:
+    return Hexagon::JMP_EQriPntneg_nv_V4;
+  case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
+    return Hexagon::JMP_EQriNotPntneg_nv_V4;
+
+  // JMP_EQrr
+  case Hexagon::JMP_EQrrPt_ie_nv_V4:
+    return Hexagon::JMP_EQrrPt_nv_V4;
+  case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
+    return Hexagon::JMP_EQrrNotPt_nv_V4;
+  case Hexagon::JMP_EQrrPnt_ie_nv_V4:
+    return Hexagon::JMP_EQrrPnt_nv_V4;
+  case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
+    return Hexagon::JMP_EQrrNotPnt_nv_V4;
+
+  // JMP_GTri
+  case Hexagon::JMP_GTriPt_ie_nv_V4:
+    return Hexagon::JMP_GTriPt_nv_V4;
+  case Hexagon::JMP_GTriNotPt_ie_nv_V4:
+    return Hexagon::JMP_GTriNotPt_nv_V4;
+  case Hexagon::JMP_GTriPnt_ie_nv_V4:
+    return Hexagon::JMP_GTriPnt_nv_V4;
+  case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
+    return Hexagon::JMP_GTriNotPnt_nv_V4;
+
+  // JMP_GTri -- with -1
+  case Hexagon::JMP_GTriPtneg_ie_nv_V4:
+    return Hexagon::JMP_GTriPtneg_nv_V4;
+  case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
+    return Hexagon::JMP_GTriNotPtneg_nv_V4;
+  case Hexagon::JMP_GTriPntneg_ie_nv_V4:
+    return Hexagon::JMP_GTriPntneg_nv_V4;
+  case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
+    return Hexagon::JMP_GTriNotPntneg_nv_V4;
+
+  // JMP_GTrr
+  case Hexagon::JMP_GTrrPt_ie_nv_V4:
+    return Hexagon::JMP_GTrrPt_nv_V4;
+  case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
+    return Hexagon::JMP_GTrrNotPt_nv_V4;
+  case Hexagon::JMP_GTrrPnt_ie_nv_V4:
+    return Hexagon::JMP_GTrrPnt_nv_V4;
+  case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
+    return Hexagon::JMP_GTrrNotPnt_nv_V4;
+
+  // JMP_GTrrdn
+  case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
+    return Hexagon::JMP_GTrrdnPt_nv_V4;
+  case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
+    return Hexagon::JMP_GTrrdnNotPt_nv_V4;
+  case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
+    return Hexagon::JMP_GTrrdnPnt_nv_V4;
+  case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
+    return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
+
+  // JMP_GTUri
+  case Hexagon::JMP_GTUriPt_ie_nv_V4:
+    return Hexagon::JMP_GTUriPt_nv_V4;
+  case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
+    return Hexagon::JMP_GTUriNotPt_nv_V4;
+  case Hexagon::JMP_GTUriPnt_ie_nv_V4:
+    return Hexagon::JMP_GTUriPnt_nv_V4;
+  case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
+    return Hexagon::JMP_GTUriNotPnt_nv_V4;
+
+  // JMP_GTUrr
+  case Hexagon::JMP_GTUrrPt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrPt_nv_V4;
+  case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrNotPt_nv_V4;
+  case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrPnt_nv_V4;
+  case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrNotPnt_nv_V4;
+
+  // JMP_GTUrrdn
+  case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrdnPt_nv_V4;
+  case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
+  case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrdnPnt_nv_V4;
+  case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
+    return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
   }
-  assert(0 && "Unknown type of jump instruction");
 }
 
 
diff --git a/lib/Target/Hexagon/HexagonMCInstLower.cpp b/lib/Target/Hexagon/HexagonMCInstLower.cpp
index fbb331b..70bddcc 100644
--- a/lib/Target/Hexagon/HexagonMCInstLower.cpp
+++ b/lib/Target/Hexagon/HexagonMCInstLower.cpp
@@ -49,7 +49,7 @@ void llvm::HexagonLowerToMC(const MachineInstr* MI, MCInst& MCI,
     switch (MO.getType()) {
     default:
       MI->dump();
-      assert(0 && "unknown operand type");
+      llvm_unreachable("unknown operand type");
     case MachineOperand::MO_Register:
       // Ignore all implicit register operands.
       if (MO.isImplicit()) continue;
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 0fe97ef..c6e7bd1 100644
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -102,7 +102,7 @@ namespace {
                           MachineDominatorTree &MDT);
 
     // initPacketizerState - initialize some internal flags.
-    void initPacketizerState(void);
+    void initPacketizerState();
 
     // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
     bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
@@ -250,7 +250,7 @@ void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
     MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
   } else {
     MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
-    assert(0 && "can not reserve resources for constant extender.");
+    llvm_unreachable("can not reserve resources for constant extender.");
   }
   return;
 }
@@ -491,6 +491,7 @@ static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
 // Return the new value instruction for a given store.
 static int GetDotNewOp(const int opc) {
   switch (opc) {
+  default: llvm_unreachable("Unknown .new type");
 
   // store new value byte
   case Hexagon::STrib:
@@ -773,16 +774,14 @@ static int GetDotNewOp(const int opc) {
 
   case Hexagon::STriw_GP_cdnNotPt_V4:
     return Hexagon::STriw_GP_cdnNotPt_nv_V4;
-
-  default:
-    assert(0 && "Unknown .new type");
   }
-  return 0;
 }
 
 // Return .new predicate version for an instruction
 static int GetDotNewPredOp(const int opc) {
   switch (opc) {
+  default: llvm_unreachable("Unknown .new type");
+
   // Conditional stores
   // Store byte conditionally
   case Hexagon::STrib_cPt :
@@ -1405,12 +1404,7 @@ static int GetDotNewPredOp(const int opc) {
     return Hexagon::ZXTH_cdnPt_V4;
   case Hexagon::ZXTH_cNotPt_V4 :
     return Hexagon::ZXTH_cdnNotPt_V4;
-
-
-  default:
-    assert(0 && "Unknown .new type");
   }
-  return 0;
 }
 
 // Returns true if an instruction can be promoted to .new predicate
@@ -1482,6 +1476,8 @@ bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
 
 static int GetDotOldOp(const int opc) {
   switch (opc) {
+  default: llvm_unreachable("Unknown .old type");
+
   case Hexagon::TFR_cdnPt:
     return Hexagon::TFR_cPt;
 
@@ -2156,11 +2152,7 @@ static int GetDotOldOp(const int opc) {
 
   case Hexagon::STrid_GP_cdnNotPt_V4 :
     return Hexagon::STrid_GP_cNotPt_V4;
-
-  default:
-    assert(0 && "Unknown .old type");
   }
-  return 0;
 }
 
 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
@@ -2761,10 +2753,7 @@ static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
   }
 #endif
   // we should never come here.
-  assert(0 && "mayLoad or mayStore not set for Post Increment operation");
-
-  // return *some value* to avoid compiler warning
-  return MI->getOperand(0);
+  llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
 }
 
 // get the value being stored
@@ -3167,7 +3156,7 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
 }
 
 // initPacketizerState - Initialize packetizer flags
-void HexagonPacketizerList::initPacketizerState(void) {
+void HexagonPacketizerList::initPacketizerState() {
 
   Dependence = false;
   PromotedToDotNew = false;
@@ -3236,10 +3225,10 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
 
   // Inline asm cannot go in the packet.
   if (I->getOpcode() == Hexagon::INLINEASM)
-    assert(0 && "Should not meet inline asm here!");
+    llvm_unreachable("Should not meet inline asm here!");
 
   if (isSoloInstruction(I))
-    assert(0 && "Should not meet solo instr here!");
+    llvm_unreachable("Should not meet solo instr here!");
 
   // A save callee-save register function call can only be in a packet
   // with instructions that don't write to the callee-save registers.
@@ -3550,8 +3539,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
 // isLegalToPruneDependencies
 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
   MachineInstr *I = SUI->getInstr();
-  MachineInstr *J = SUJ->getInstr();
-  assert(I && J && "Unable to packetize null instruction!");
+  assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
 
   const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
 
diff --git a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
index f78965e..75d6bfb 100644
--- a/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
+++ b/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
@@ -144,24 +144,21 @@ void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
 
 void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
                                             raw_ostream &O) const {
-  const MCOperand& MO = MI->getOperand(OpNo);
-  assert(MO.isExpr() && "Expecting expression");
+  assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
 
   printOperand(MI, OpNo, O);
 }
 
 void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
                                         raw_ostream &O) const {
-  const MCOperand& MO = MI->getOperand(OpNo);
-  assert(MO.isExpr() && "Expecting expression");
+  assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
 
   printOperand(MI, OpNo, O);
 }
 
 void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
                                            raw_ostream &O) const {
-  const MCOperand& MO = MI->getOperand(OpNo);
-  assert(MO.isExpr() && "Expecting expression");
+  assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
 
   printOperand(MI, OpNo, O);
 }