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| author | Evan Cheng <evan.cheng@apple.com> | 2008-03-26 08:11:49 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-03-26 08:11:49 +0000 |
| commit | 7aae876db13b76a10d690777d93e11093a15c826 (patch) | |
| tree | 3a614e14b2cf7c2e9be248da6892b645096554e1 /lib | |
| parent | d382f8a32de02e04db5f88e881fe11db4040be40 (diff) | |
| download | external_llvm-7aae876db13b76a10d690777d93e11093a15c826.zip external_llvm-7aae876db13b76a10d690777d93e11093a15c826.tar.gz external_llvm-7aae876db13b76a10d690777d93e11093a15c826.tar.bz2 | |
Fix some SSE4.1 instruction encoding bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48815 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 9a3b2f6..7d70480 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3327,7 +3327,7 @@ defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>; /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> { - def rr : SS4AIi8<opc, MRMSrcReg, (outs GR32:$dst), + def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), @@ -3363,7 +3363,7 @@ defm PEXTRW : SS41I_extract16<0x15, "pextrw">; /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> { - def rr : SS4AIi8<opc, MRMSrcReg, (outs GR32:$dst), + def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), @@ -3384,7 +3384,7 @@ defm PEXTRD : SS41I_extract32<0x16, "pextrd">; /// destination multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> { // Not worth matching to rr form of extractps since the result is in GPR32. - def rr : SS4AIi8<opc, MRMSrcReg, (outs GR32:$dst), + def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), @@ -3460,7 +3460,7 @@ let Constraints = "$src1 = $dst" in { } } -defm INSERTPS : SS41I_insertf32<0x31, "insertps">; +defm INSERTPS : SS41I_insertf32<0x21, "insertps">; let Defs = [EFLAGS] in { def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2), |