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| author | Johnny Chen <johnny.chen@apple.com> | 2010-08-11 23:35:12 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-08-11 23:35:12 +0000 |
| commit | 7def14f40f0b47551e2d66ec2f140a18b5bbbea4 (patch) | |
| tree | a60a441916ab0b7c225be06a3f81ba6ed1f838ba /lib | |
| parent | ebd53742c6ce51edb46dfd0a477c03d7770a1818 (diff) | |
| download | external_llvm-7def14f40f0b47551e2d66ec2f140a18b5bbbea4.zip external_llvm-7def14f40f0b47551e2d66ec2f140a18b5bbbea4.tar.gz external_llvm-7def14f40f0b47551e2d66ec2f140a18b5bbbea4.tar.bz2 | |
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
Added two test cases to arm-tests.txt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h | 4 |
3 files changed, 6 insertions, 9 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 827b743..f058ee1 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -2356,7 +2356,7 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst), // memory barriers protect the atomic sequences let hasSideEffects = 1 in { -def DMBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dmb", "", +def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "", [(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> { let Inst{31-4} = 0xf57ff05; // FIXME: add support for options other than a full system DMB @@ -2364,7 +2364,7 @@ def DMBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dmb", "", let Inst{3-0} = 0b1111; } -def DSBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dsb", "", +def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "", [(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> { let Inst{31-4} = 0xf57ff04; // FIXME: add support for options other than a full system DSB @@ -2372,7 +2372,7 @@ def DSBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dsb", "", let Inst{3-0} = 0b1111; } -def DMB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary, +def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary, "mcr", "\tp15, 0, $zero, c7, c10, 5", [(ARMMemBarrierMCR GPR:$zero)]>, Requires<[IsARM, HasV6]> { @@ -2380,7 +2380,7 @@ def DMB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary, // FIXME: add encoding } -def DSB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary, +def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary, "mcr", "\tp15, 0, $zero, c7, c10, 4", [(ARMSyncBarrierMCR GPR:$zero)]>, Requires<[IsARM, HasV6]> { diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index 57dc347..39d7c52 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -493,9 +493,6 @@ static inline ARM_AM::AMSubMode getAMSubModeForBits(unsigned bits) { static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO) { - if (Opcode == ARM::DMBsy || Opcode == ARM::DSBsy) - return true; - assert(0 && "Unexpected pseudo instruction!"); return false; } diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h index 2bdb1537..43152fa 100644 --- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h +++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h @@ -1629,8 +1629,8 @@ static inline bool t2MiscCtrlInstr(uint32_t insn) { // A8.6.26 // t2BXJ -> Rn // -// Miscellaneous control: t2Int_MemBarrierV7 (and its t2DMB variants), -// t2Int_SyncBarrierV7 (and its t2DSB varianst), t2ISBsy, t2CLREX +// Miscellaneous control: t2DMBsy (and its t2DMB variants), +// t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX // -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants) // // Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV |