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| author | Eli Friedman <eli.friedman@gmail.com> | 2011-12-15 23:46:18 +0000 |
|---|---|---|
| committer | Eli Friedman <eli.friedman@gmail.com> | 2011-12-15 23:46:18 +0000 |
| commit | 7e840efc238db1123ea625b3d4e9893d6ea1bc50 (patch) | |
| tree | 0e131ab2699e2dede8cea065fe347805838728c4 /lib | |
| parent | bcf14bbd57b8457ea09afbfc7acddf2d21a5adac (diff) | |
| download | external_llvm-7e840efc238db1123ea625b3d4e9893d6ea1bc50.zip external_llvm-7e840efc238db1123ea625b3d4e9893d6ea1bc50.tar.gz external_llvm-7e840efc238db1123ea625b3d4e9893d6ea1bc50.tar.bz2 | |
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146709 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/X86InstrFormats.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index 631e9bc..7ba3639 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -510,7 +510,7 @@ class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm, // FMA4 Instruction Templates class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag>pattern> - : I<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, + : Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TA, OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>; // XOP 2, 3 and 4 Operand Instruction Template diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 8c16fe5..345f606 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -6563,14 +6563,14 @@ let Constraints = "$src1 = $dst" in { multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr, RegisterClass RC, X86MemOperand x86memop, PatFrag mem_frag, Intrinsic IntId> { - def rr : I<opc, MRMSrcReg, (outs RC:$dst), + def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM; - def rm : I<opc, MRMSrcMem, (outs RC:$dst), + def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, RC:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), |