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| author | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-08-12 13:07:23 +0000 |
|---|---|---|
| committer | Vladimir Medic <Vladimir.Medic@imgtec.com> | 2013-08-12 13:07:23 +0000 |
| commit | 809313970fc98bba6f36a332adfa3e5fef4110b3 (patch) | |
| tree | 1620db87768204660ebce15615e016b652ea1ab2 /lib | |
| parent | dcef6a7400d51526a04a18e274bd579da262e9ad (diff) | |
| download | external_llvm-809313970fc98bba6f36a332adfa3e5fef4110b3.zip external_llvm-809313970fc98bba6f36a332adfa3e5fef4110b3.tar.gz external_llvm-809313970fc98bba6f36a332adfa3e5fef4110b3.tar.bz2 | |
This patch implements ei and di instructions for mips. Test cases are added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188176 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/Mips/MipsInstrFormats.td | 18 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 13 |
2 files changed, 30 insertions, 1 deletions
diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 1322784..28abb7e 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -520,6 +520,24 @@ class ER_FM<bits<6> funct> let Inst{5-0} = funct; } + +//===----------------------------------------------------------------------===// +// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0> +//===----------------------------------------------------------------------===// + +class EI_FM<bits<1> sc> +{ + bits<32> Inst; + bits<5> rt; + let Inst{31-26} = 0x10; + let Inst{25-21} = 0xb; + let Inst{20-16} = rt; + let Inst{15-11} = 0xc; + let Inst{10-6} = 0; + let Inst{5} = sc; + let Inst{4-0} = 0; +} + //===----------------------------------------------------------------------===// // // FLOATING POINT INSTRUCTION FORMATS diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index c321330..65601b0 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -660,6 +660,11 @@ class ER_FT<string opstr> : InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther>; +// Interrupts +class DEI_FT<string opstr, RegisterOperand RO> : + InstSE<(outs RO:$rt), (ins), + !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>; + // Sync let hasSideEffects = 1 in class SYNC_FT : @@ -953,7 +958,8 @@ defm LBu : LoadM<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel, defm LH : LoadM<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel, LW_FM<0x21>; defm LHu : LoadM<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>; -defm LW : LoadM<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, LW_FM<0x23>; +defm LW : LoadM<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel, + LW_FM<0x23>; defm SB : StoreM<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>; defm SH : StoreM<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>; defm SW : StoreM<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>; @@ -973,6 +979,9 @@ def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>; def ERET : ER_FT<"eret">, ER_FM<0x18>; def DERET : ER_FT<"deret">, ER_FM<0x1f>; +def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>; +def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>; + /// Load-linked, Store-conditional let Predicates = [NotN64, HasStdEnc] in { def LL : LLBase<"ll", GPR32Opnd, mem>, LW_FM<0x30>; @@ -1145,6 +1154,8 @@ def : InstAlias<"syscall", (SYSCALL 0), 1>; def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; def : InstAlias<"break", (BREAK 0, 0), 1>; +def : InstAlias<"ei", (EI ZERO), 1>; +def : InstAlias<"di", (DI ZERO), 1>; //===----------------------------------------------------------------------===// // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// |