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author | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 04:08:42 +0000 |
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committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-09-27 04:08:42 +0000 |
commit | 833f7a5c4b77796d1ad739b8d92d824612cd819e (patch) | |
tree | bf27848bbbed0ffe9b794c934bd05bfba6874db9 /lib | |
parent | 451b0e7b8a56457114d8989ac836163d82a1cf5e (diff) | |
download | external_llvm-833f7a5c4b77796d1ad739b8d92d824612cd819e.zip external_llvm-833f7a5c4b77796d1ad739b8d92d824612cd819e.tar.gz external_llvm-833f7a5c4b77796d1ad739b8d92d824612cd819e.tar.bz2 |
MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164756 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Mips/MipsDSPInstrFormats.td | 12 | ||||
-rw-r--r-- | lib/Target/Mips/MipsDSPInstrInfo.td | 14 |
2 files changed, 26 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsDSPInstrFormats.td b/lib/Target/Mips/MipsDSPInstrFormats.td index 9e96bdf..2c6e767 100644 --- a/lib/Target/Mips/MipsDSPInstrFormats.td +++ b/lib/Target/Mips/MipsDSPInstrFormats.td @@ -174,6 +174,18 @@ class SHILO_R2_FMT<bits<5> op> : DSPInst { let Inst{5-0} = 0b111000; } +class RDDSP_FMT<bits<5> op> : DSPInst { + bits<5> rd; + bits<10> mask; + + let Opcode = SPECIAL3_OPCODE.V; + + let Inst{25-16} = mask; + let Inst{15-11} = rd; + let Inst{10-6} = op; + let Inst{5-0} = 0b111000; +} + class BPOSGE32_FMT<bits<5> op> : DSPInst { bits<16> offset; diff --git a/lib/Target/Mips/MipsDSPInstrInfo.td b/lib/Target/Mips/MipsDSPInstrInfo.td index 332a371..91f8ab1 100644 --- a/lib/Target/Mips/MipsDSPInstrInfo.td +++ b/lib/Target/Mips/MipsDSPInstrInfo.td @@ -164,6 +164,7 @@ class SHILO_ENC : SHILO_R1_FMT<0b11010>; class SHILOV_ENC : SHILO_R2_FMT<0b11011>; class MTHLIP_ENC : SHILO_R2_FMT<0b11111>; +class RDDSP_ENC : RDDSP_FMT<0b10010>; class ADDU_PH_ENC : ADDU_QB_FMT<0b01000>; class ADDU_S_PH_ENC : ADDU_QB_FMT<0b01100>; class SUBU_PH_ENC : ADDU_QB_FMT<0b01001>; @@ -296,6 +297,16 @@ class MTHLIP_DESC_BASE<string instr_asm> { string AsmString = !strconcat(instr_asm, "\t$rs, $ac"); } +class RDDSP_DESC_BASE<string instr_asm, SDPatternOperator OpNode, + InstrItinClass itin> { + dag OutOperandList = (outs CPURegs:$rd); + dag InOperandList = (ins uimm16:$mask); + string AsmString = !strconcat(instr_asm, "\t$rd, $mask"); + list<dag> Pattern = [(set CPURegs:$rd, (OpNode immZExt10:$mask))]; + InstrItinClass Itinerary = itin; + list<Register> Uses = [DSPCtrl]; +} + class DPA_W_PH_PSEUDO_BASE<SDPatternOperator OpNode, InstrItinClass itin, Instruction realinst> : PseudoDSP<(outs), (ins CPURegs:$rs, CPURegs:$rt), @@ -573,6 +584,8 @@ class SHILOV_DESC : SHILO_R2_DESC_BASE<"shilov">; class MTHLIP_DESC : MTHLIP_DESC_BASE<"mthlip">; +class RDDSP_DESC : RDDSP_DESC_BASE<"rddsp", int_mips_rddsp, NoItinerary>; + //===----------------------------------------------------------------------===// // MIPS DSP Rev 2 // Addition/subtraction @@ -719,6 +732,7 @@ def EXTRV_S_H : EXTRV_S_H_ENC, EXTRV_S_H_DESC; def SHILO : SHILO_ENC, SHILO_DESC; def SHILOV : SHILOV_ENC, SHILOV_DESC; def MTHLIP : MTHLIP_ENC, MTHLIP_DESC; +def RDDSP : RDDSP_ENC, RDDSP_DESC; // MIPS DSP Rev 2 let Predicates = [HasDSPR2] in { |