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authorAlexey Samsonov <samsonov@google.com>2013-08-15 07:11:34 +0000
committerAlexey Samsonov <samsonov@google.com>2013-08-15 07:11:34 +0000
commit84e51517e25119419d53d6ed61fef15219efd733 (patch)
tree1fe0aaa359b9109e8c1600eba9ebec5e84a44d4a /lib
parent07ad0c4c99cb704d4f3e1bc1ba3bb1b194efe572 (diff)
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Tentative fix for global-buffer-overflow caused by r188426. Found by AddressSanitizer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188448 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/R600/AMDGPUISelDAGToDAG.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
index 22bdb90..77ca885 100644
--- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
@@ -115,7 +115,10 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
switch (N->getMachineOpcode()) {
default: {
const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
- int RegClass = Desc.OpInfo[Desc.getNumDefs() + OpNo].RegClass;
+ unsigned OpIdx = Desc.getNumDefs() + OpNo;
+ if (OpIdx >= Desc.getNumOperands())
+ return NULL;
+ int RegClass = Desc.OpInfo[OpIdx].RegClass;
if (RegClass == -1) {
return NULL;
}