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| author | Chris Lattner <sabre@nondot.org> | 2004-04-12 01:43:36 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2004-04-12 01:43:36 +0000 |
| commit | 8d2822e7f180ce88b19c8dfcdadd0a4bc2b0a3b9 (patch) | |
| tree | 325d77b39126398f9aa552b5360b0a75c50f2555 /lib | |
| parent | c040bca4b9dfaa58cbc0c00f1cc435e3251332ec (diff) | |
| download | external_llvm-8d2822e7f180ce88b19c8dfcdadd0a4bc2b0a3b9.zip external_llvm-8d2822e7f180ce88b19c8dfcdadd0a4bc2b0a3b9.tar.gz external_llvm-8d2822e7f180ce88b19c8dfcdadd0a4bc2b0a3b9.tar.bz2 | |
Use the fucomi[p] instructions to perform floating point comparisons instead
of the fucom[p][p] instructions. This allows us to code generate this function
bool %test(double %X, double %Y) {
%C = setlt double %Y, %X
ret bool %C
}
... into:
test:
fld QWORD PTR [%ESP + 4]
fld QWORD PTR [%ESP + 12]
fucomip %ST(1)
fstp %ST(0)
setb %AL
movsx %EAX, %AL
ret
where before we generated:
test:
fld QWORD PTR [%ESP + 4]
fld QWORD PTR [%ESP + 12]
fucompp
** fnstsw
** sahf
setb %AL
movsx %EAX, %AL
ret
The two marked instructions (which are the ones eliminated) are very bad,
because they serialize execution of the processor. These instructions are
available on the PPRO and later, but since we already use cmov's we aren't
losing any portability.
I retained the old code for the day when we decide we want to support back
to the 386.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12852 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 10 |
2 files changed, 14 insertions, 6 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index a2e7e66..c8802ed 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -929,9 +929,13 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r); break; case cFP: - BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r); - BuildMI(*MBB, IP, X86::FNSTSW8r, 0); - BuildMI(*MBB, IP, X86::SAHF, 1); + if (0) { // for processors prior to the P6 + BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::FNSTSW8r, 0); + BuildMI(*MBB, IP, X86::SAHF, 1); + } else { + BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(Op0r).addReg(Op1r); + } break; case cLong: diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index a2e7e66..c8802ed 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -929,9 +929,13 @@ unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1, BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r); break; case cFP: - BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r); - BuildMI(*MBB, IP, X86::FNSTSW8r, 0); - BuildMI(*MBB, IP, X86::SAHF, 1); + if (0) { // for processors prior to the P6 + BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r); + BuildMI(*MBB, IP, X86::FNSTSW8r, 0); + BuildMI(*MBB, IP, X86::SAHF, 1); + } else { + BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(Op0r).addReg(Op1r); + } break; case cLong: |