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author | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-05 11:59:43 +0000 |
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committer | Tilmann Scheller <tilmann.scheller@googlemail.com> | 2013-09-05 11:59:43 +0000 |
commit | 8f3d54d057007552d0abc37c87a50ef34a7ab9ef (patch) | |
tree | 640d07133c8f2ab9f909e7b2c464f96e6c1a5496 /lib | |
parent | 10b5086e6e945b830ff909821240eff5c4a42bfc (diff) | |
download | external_llvm-8f3d54d057007552d0abc37c87a50ef34a7ab9ef.zip external_llvm-8f3d54d057007552d0abc37c87a50ef34a7ab9ef.tar.gz external_llvm-8f3d54d057007552d0abc37c87a50ef34a7ab9ef.tar.bz2 |
Reverting 190043 for now.
Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code.
Test case doesn't trigger the added functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 | ||||
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 8 | ||||
-rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 16 |
3 files changed, 3 insertions, 23 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 2f3fa63..5d0c484 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1233,7 +1233,7 @@ let neverHasSideEffects = 1, isReMaterializable = 1 in def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; let hasSideEffects = 1 in -def t2LEApcrelJT : t2PseudoInst<(outs jtGPR:$Rd), +def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, nohash_imm:$id, pred:$p), 4, IIC_iALUi, []>, Sched<[WriteALU, ReadALU]>; diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 51ecaf7..90c6a96 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -240,14 +240,6 @@ def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> { }]; } -// jtGPR - Jump Table General Purpose Registers. -// Used by the Thumb2 instructions to prevent Thumb2 jump tables -// from using the LR. The implementation of the jump table uses a mov pc, rA -// type instruction to jump into the table. Use of the LR register (as in -// mov pc, lr) can cause the ARM branch predictor to think it is returning -// from a function instead. This causes a mispredict and a pipe flush. -def jtGPR : RegisterClass<"ARM", [i32], 32, (sub rGPR, LR)>; - // Thumb registers are R0-R7 normally. Some instructions can still use // the general GPR register class above (MOV, e.g.) def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>; diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index 7c51c70..286eaa0 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -152,13 +152,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, // gsub_0, but needs an extra constraint for gsub_1 (which could be sp // otherwise). MachineRegisterInfo *MRI = &MF.getRegInfo(); - const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC, - &ARM::rGPRRegClass, - ARM::gsub_1); - assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass"); - const TargetRegisterClass* ConstrainedClass = - MRI->constrainRegClass(SrcReg, TargetClass); - assert(ConstrainedClass && "Couldn't constrain the register class"); + MRI->constrainRegClass(SrcReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8)); AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); @@ -199,13 +193,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, // gsub_0, but needs an extra constraint for gsub_1 (which could be sp // otherwise). MachineRegisterInfo *MRI = &MF.getRegInfo(); - const TargetRegisterClass* TargetClass = TRI->getMatchingSuperRegClass(RC, - &ARM::rGPRRegClass, - ARM::gsub_1); - assert(TargetClass && "No Matching GPRPair with gsub_1 in rGPRRegClass"); - const TargetRegisterClass* ConstrainedClass = - MRI->constrainRegClass(DestReg, TargetClass); - assert(ConstrainedClass && "Couldn't constrain the register class"); + MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8)); AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); |