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author | Dan Gohman <gohman@apple.com> | 2009-03-24 00:50:07 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2009-03-24 00:50:07 +0000 |
commit | 8f4aa333d02d0f48f90f4604d894a73ee53edcb5 (patch) | |
tree | 18c0b12a965bea6879811aff70c665940107ade7 /lib | |
parent | 002b44f1d7c0b301b78dec1f24d406d4b351fdaa (diff) | |
download | external_llvm-8f4aa333d02d0f48f90f4604d894a73ee53edcb5.zip external_llvm-8f4aa333d02d0f48f90f4604d894a73ee53edcb5.tar.gz external_llvm-8f4aa333d02d0f48f90f4604d894a73ee53edcb5.tar.bz2 |
Minor compile-time optimization; don't bother checking
canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 39c4f4e..30dc476 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1392,7 +1392,7 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() { continue; // Don't constrain nodes with physical register defs if the // predecessor can clobber them. - if (SuccSU->hasPhysRegDefs) { + if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) { if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI)) continue; } |