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authorRichard Osborne <richard@xmos.com>2011-08-24 13:32:43 +0000
committerRichard Osborne <richard@xmos.com>2011-08-24 13:32:43 +0000
commit8f9c5cca4feb71471dda44d9ba39a0ca644ddd6e (patch)
tree2131bf8ff367cddba88d44f7ccd78f870f1c2581 /lib
parent13894fa135d33151072ddf5e80abe4540ec2afcd (diff)
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Add Uses=[SP] to call instructions. This fixes a miscompilation with a
variable sized alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index a1ec8aa..a960469 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -739,7 +739,7 @@ def LDAP_lu10_ba : _FLU10<(outs),
let isCall=1,
// All calls clobber the link register and the non-callee-saved registers:
-Defs = [R0, R1, R2, R3, R11, LR] in {
+Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
def BL_u10 : _FU10<
(outs),
(ins calltarget:$target, variable_ops),
@@ -981,7 +981,7 @@ def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src),
let isCall=1,
// All calls clobber the link register and the non-callee-saved registers:
-Defs = [R0, R1, R2, R3, R11, LR] in {
+Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
"bla $addr",
[(XCoreBranchLink GRRegs:$addr)]>;