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author | Anton Korobeynikov <asl@math.spbu.ru> | 2007-11-15 23:25:33 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2007-11-15 23:25:33 +0000 |
commit | 917c2a6ff2cfcd1263a5dd80c54336754c553ace (patch) | |
tree | 0bdf888ec6dc60c6593bcce3ba60a8d446bcc9ed /lib | |
parent | 5db1afb462b048bc10e0003db5a770ed960b2ddf (diff) | |
download | external_llvm-917c2a6ff2cfcd1263a5dd80c54336754c553ace.zip external_llvm-917c2a6ff2cfcd1263a5dd80c54336754c553ace.tar.gz external_llvm-917c2a6ff2cfcd1263a5dd80c54336754c553ace.tar.bz2 |
Implement necessary bits for flt_rounds gcc builtin.
Codegen bits and llvm-gcc support will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44182 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/IntrinsicLowering.cpp | 5 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 14 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 1 | ||||
-rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 |
4 files changed, 24 insertions, 0 deletions
diff --git a/lib/CodeGen/IntrinsicLowering.cpp b/lib/CodeGen/IntrinsicLowering.cpp index bd3d74d..0d1da86 100644 --- a/lib/CodeGen/IntrinsicLowering.cpp +++ b/lib/CodeGen/IntrinsicLowering.cpp @@ -856,6 +856,11 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) { } break; } + case Intrinsic::flt_rounds: + // Lower to "round to the nearest" + if (CI->getType() != Type::VoidTy) + CI->replaceAllUsesWith(ConstantInt::get(CI->getType(), 1)); + break; } assert(CI->use_empty() && diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 9c0c845..d17fbea 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3677,6 +3677,20 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { AddLegalizedOperand(SDOperand(Node, 1), Tmp1); return Op.ResNo ? Tmp1 : Result; } + case ISD::FLT_ROUNDS: { + MVT::ValueType VT = Node->getValueType(0); + switch (TLI.getOperationAction(Node->getOpcode(), VT)) { + default: assert(0 && "This action not supported for this op yet!"); + case TargetLowering::Custom: + Result = TLI.LowerOperation(Op, DAG); + if (Result.Val) break; + // Fall Thru + case TargetLowering::Legal: + // If this operation is not supported, lower it to constant 1 + Result = DAG.getConstant(1, VT); + break; + } + } } assert(Result.getValueType() == Op.getValueType() && diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index d92bb9c..38987d9 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3739,6 +3739,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg"; case ISD::TRUNCATE: return "truncate"; case ISD::FP_ROUND: return "fp_round"; + case ISD::FLT_ROUNDS: return "flt_rounds"; case ISD::FP_ROUND_INREG: return "fp_round_inreg"; case ISD::FP_EXTEND: return "fp_extend"; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index c078f23..ade0a28 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -2930,6 +2930,10 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { DAG.setRoot(Tmp.getValue(1)); return 0; } + case Intrinsic::flt_rounds: { + setValue(&I, DAG.getNode(ISD::FLT_ROUNDS, MVT::i32)); + return 0; + } } } |