getOpCode() --> getOpcode().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11339 91177308-0d34-0410-b5e6-96231b3b80d8

8 files changed, 106 insertions, 106 deletions

diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 9cec481..7d2ecec 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -424,7 +424,7 @@ public:
     // Append the instruction to the vector of choices for current cycle.
     // Increment numInClass[c] for the sched class to which the instr belongs.
     choiceVec.push_back(node);
-    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
+    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
     assert(sc < numInClass.size());
     numInClass[sc]++;
   }
@@ -478,7 +478,7 @@ public:
       choicesForSlot[s].erase(node);
     
     // and decrement the instr count for the sched class to which it belongs
-    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
+    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
     assert(sc < numInClass.size());
     numInClass[sc]--;
   }
@@ -498,7 +498,7 @@ public:
     if (!createIfMissing) return 0;
 
     DelaySlotInfo *dinfo =
-      new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpCode()));
+      new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpcode()));
     return delaySlotInfoForBranches[bn] = dinfo;
   }
   
@@ -537,19 +537,19 @@ void
 SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
 					    cycles_t schedTime)
 {
-  if (schedInfo.numBubblesAfter(node->getOpCode()) > 0)
+  if (schedInfo.numBubblesAfter(node->getOpcode()) > 0)
     { // Update next earliest time before which *nothing* can issue.
       nextEarliestIssueTime = std::max(nextEarliestIssueTime,
-		  curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
+		  curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
     }
   
   const std::vector<MachineOpCode>&
-    conflictVec = schedInfo.getConflictList(node->getOpCode());
+    conflictVec = schedInfo.getConflictList(node->getOpcode());
   
   for (unsigned i=0; i < conflictVec.size(); i++)
     {
       MachineOpCode toOp = conflictVec[i];
-      cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpCode(),toOp);
+      cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpcode(),toOp);
       assert(toOp < (int) nextEarliestStartTime.size());
       if (nextEarliestStartTime[toOp] < est)
         nextEarliestStartTime[toOp] = est;
@@ -630,8 +630,8 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   // some NOPs from delay slots.  Also, PHIs are not included in the schedule.
   unsigned numInstr = 0;
   for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
-    if (! mii.isNop((*I)->getOpCode()) &&
-	! mii.isDummyPhiInstr((*I)->getOpCode()))
+    if (! mii.isNop((*I)->getOpcode()) &&
+	! mii.isDummyPhiInstr((*I)->getOpcode()))
       ++numInstr;
   assert(S.isched.getNumInstructions() >= numInstr &&
 	 "Lost some non-NOP instructions during scheduling!");
@@ -643,7 +643,7 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   // First find the dummy instructions at the start of the basic block
   MachineBasicBlock::iterator I = MBB.begin();
   for ( ; I != MBB.end(); ++I)
-    if (! mii.isDummyPhiInstr((*I)->getOpCode()))
+    if (! mii.isDummyPhiInstr((*I)->getOpcode()))
       break;
   
   // Erase all except the dummy PHI instructions from MBB, and
@@ -726,7 +726,7 @@ FindSlotChoices(SchedulingManager& S,
     if (nextNode == NULL)
       break;			// no more instructions for this cycle
       
-    if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0) {
+    if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) {
       delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
       if (delaySlotInfo != NULL) {
         if (indexForBreakingNode < S.nslots)
@@ -736,7 +736,7 @@ FindSlotChoices(SchedulingManager& S,
         else
           indexForDelayedInstr = S.getNumChoices();
       }
-    } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode())) {
+    } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpcode())) {
       if (indexForBreakingNode < S.nslots)
         // have a breaking instruction already so throw this one away
         nextNode = NULL;
@@ -747,7 +747,7 @@ FindSlotChoices(SchedulingManager& S,
     if (nextNode != NULL) {
       S.addChoice(nextNode);
       
-      if (S.schedInfo.isSingleIssue(nextNode->getOpCode())) {
+      if (S.schedInfo.isSingleIssue(nextNode->getOpcode())) {
         assert(S.getNumChoices() == 1 &&
                "Prioritizer returned invalid instr for this cycle!");
         break;
@@ -772,7 +772,7 @@ FindSlotChoices(SchedulingManager& S,
     // This is the common case, so handle it separately for efficiency.
       
     if (S.getNumChoices() == 1) {
-      MachineOpCode opCode = S.getChoice(0)->getOpCode();
+      MachineOpCode opCode = S.getChoice(0)->getOpcode();
       unsigned int s;
       for (s=startSlot; s < S.nslots; s++)
         if (S.schedInfo.instrCanUseSlot(opCode, s))
@@ -781,7 +781,7 @@ FindSlotChoices(SchedulingManager& S,
       S.addChoiceToSlot(s, S.getChoice(0));
     } else {
       for (unsigned i=0; i < S.getNumChoices(); i++) {
-        MachineOpCode opCode = S.getChoice(i)->getOpCode();
+        MachineOpCode opCode = S.getChoice(i)->getOpcode();
         for (unsigned int s=startSlot; s < S.nslots; s++)
           if (S.schedInfo.instrCanUseSlot(opCode, s))
             S.addChoiceToSlot(s, S.getChoice(i));
@@ -799,7 +799,7 @@ FindSlotChoices(SchedulingManager& S,
     assert(delaySlotInfo != NULL && "No delay slot info for instr?");
       
     const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
-    MachineOpCode delayOpCode = delayedNode->getOpCode();
+    MachineOpCode delayOpCode = delayedNode->getOpcode();
     unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
       
     unsigned delayedNodeSlot = S.nslots;
@@ -817,7 +817,7 @@ FindSlotChoices(SchedulingManager& S,
     for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
       // Try to assign every other instruction to a lower numbered
       // slot than delayedNodeSlot.
-      MachineOpCode opCode =S.getChoice(i)->getOpCode();
+      MachineOpCode opCode =S.getChoice(i)->getOpcode();
       bool noSlotFound = true;
       unsigned int s;
       for (s=startSlot; s < delayedNodeSlot; s++)
@@ -867,7 +867,7 @@ FindSlotChoices(SchedulingManager& S,
 	  
     // Find the last possible slot for this instruction.
     for (int s = S.nslots-1; s >= (int) startSlot; s--)
-      if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s)) {
+      if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
         breakingSlot = s;
         break;
       }
@@ -880,7 +880,7 @@ FindSlotChoices(SchedulingManager& S,
     for (unsigned i=0;
          i < S.getNumChoices() && i < indexForBreakingNode; i++)
     {
-      MachineOpCode opCode =S.getChoice(i)->getOpCode();
+      MachineOpCode opCode =S.getChoice(i)->getOpcode();
 	  
       // If a higher priority instruction cannot be assigned to
       // any earlier slots, don't schedule the breaking instruction.
@@ -914,7 +914,7 @@ FindSlotChoices(SchedulingManager& S,
     // group, only assign them to slots lower than the breaking slot.
     // Otherwise, just ignore the instruction.
     for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) {
-      MachineOpCode opCode = S.getChoice(i)->getOpCode();
+      MachineOpCode opCode = S.getChoice(i)->getOpcode();
       for (unsigned int s=startSlot; s < nslotsToUse; s++)
         if (S.schedInfo.instrCanUseSlot(opCode, s))
           S.addChoiceToSlot(s, S.getChoice(i));
@@ -1026,11 +1026,11 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
   assert(! node->isDummyNode());
   
   // don't put a branch in the delay slot of another branch
-  if (S.getInstrInfo().isBranch(node->getOpCode()))
+  if (S.getInstrInfo().isBranch(node->getOpcode()))
     return false;
   
   // don't put a single-issue instruction in the delay slot of a branch
-  if (S.schedInfo.isSingleIssue(node->getOpCode()))
+  if (S.schedInfo.isSingleIssue(node->getOpcode()))
     return false;
   
   // don't put a load-use dependence in the delay slot of a branch
@@ -1039,13 +1039,13 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
   for (SchedGraphNode::const_iterator EI = node->beginInEdges();
        EI != node->endInEdges(); ++EI)
     if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode()
-	&& mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpCode())
+	&& mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
 	&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
       return false;
   
   // for now, don't put an instruction that does not have operand
   // interlocks in the delay slot of a branch
-  if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
+  if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
     return false;
   
   // Finally, if the instruction precedes the branch, we make sure the
@@ -1102,7 +1102,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
 {
   const TargetInstrInfo& mii = S.getInstrInfo();
   unsigned ndelays =
-    mii.getNumDelaySlots(brNode->getOpCode());
+    mii.getNumDelaySlots(brNode->getOpcode());
   
   if (ndelays == 0)
     return;
@@ -1117,10 +1117,10 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
   for (sg_pred_iterator P = pred_begin(brNode);
        P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
     if (! (*P)->isDummyNode() &&
-	! mii.isNop((*P)->getOpCode()) &&
+	! mii.isNop((*P)->getOpcode()) &&
 	NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
     {
-      if (mii.maxLatency((*P)->getOpCode()) > 1)
+      if (mii.maxLatency((*P)->getOpcode()) > 1)
         mdelayNodeVec.push_back(*P);
       else
         sdelayNodeVec.push_back(*P);
@@ -1133,12 +1133,12 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
   // 
   while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
     unsigned lmin =
-      mii.maxLatency(mdelayNodeVec[0]->getOpCode());
+      mii.maxLatency(mdelayNodeVec[0]->getOpcode());
     unsigned minIndex   = 0;
     for (unsigned i=1; i < mdelayNodeVec.size(); i++)
     {
       unsigned li = 
-        mii.maxLatency(mdelayNodeVec[i]->getOpCode());
+        mii.maxLatency(mdelayNodeVec[i]->getOpcode());
       if (lmin >= li)
       {
         lmin = li;
@@ -1166,7 +1166,7 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
   std::vector<SchedGraphNode*> nopNodeVec;   // this will hold unused NOPs
   const TargetInstrInfo& mii = S.getInstrInfo();
   const MachineInstr* brInstr = node->getMachineInstr();
-  unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
+  unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpcode());
   assert(ndelays > 0 && "Unnecessary call to replace NOPs");
   
   // Remove the NOPs currently in delay slots from the graph.
@@ -1182,14 +1182,14 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
   // and USE THEM.  We'll throw away the unused alternatives below
   // 
   for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
-    if (! mii.isNop(MBB[i]->getOpCode()))
+    if (! mii.isNop(MBB[i]->getOpcode()))
       sdelayNodeVec.insert(sdelayNodeVec.begin(),
                            graph->getGraphNodeForInstr(MBB[i]));
   
   // Then find the NOPs and keep only as many as are needed.
   // Put the rest in nopNodeVec to be deleted.
   for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
-    if (mii.isNop(MBB[i]->getOpCode()))
+    if (mii.isNop(MBB[i]->getOpcode()))
       if (sdelayNodeVec.size() < ndelays)
         sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
       else {
@@ -1256,7 +1256,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
     // 
     unsigned first = 0;
     while (first < termMvec.size() &&
-           ! mii.isBranch(termMvec[first]->getOpCode()))
+           ! mii.isBranch(termMvec[first]->getOpcode()))
     {
       ++first;
     }
@@ -1283,7 +1283,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
   delayNodeVec.clear();
   for (unsigned i=0; i < MBB.size(); ++i)
     if (MBB[i] != brInstr &&
-        mii.getNumDelaySlots(MBB[i]->getOpCode()) > 0)
+        mii.getNumDelaySlots(MBB[i]->getOpcode()) > 0)
     {
       SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
       ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
@@ -1321,10 +1321,10 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
     for (unsigned i=0; i < delayNodeVec.size(); i++) {
       const SchedGraphNode* dnode = delayNodeVec[i];
       if ( ! S.isScheduled(dnode)
-           && S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
-           && instrIsFeasible(S, dnode->getOpCode()))
+           && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
+           && instrIsFeasible(S, dnode->getOpcode()))
       {
-        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpCode())
+        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
                && "Instructions without interlocks not yet supported "
                "when filling branch delay slots");
         S.scheduleInstr(dnode, nextSlot, nextTime);
diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 65f1511..fe150c2 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -55,7 +55,7 @@ SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
                                int   indexInBB, const TargetMachine& Target)
   : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
   if (MI) {
-    MachineOpCode mopCode = MI->getOpCode();
+    MachineOpCode mopCode = MI->getOpcode();
     latency = Target.getInstrInfo().hasResultInterlock(mopCode)
       ? Target.getInstrInfo().minLatency(mopCode)
       : Target.getInstrInfo().maxLatency(mopCode);
@@ -140,8 +140,8 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
   // Find the first branch instr in the sequence of machine instrs for term
   // 
   unsigned first = 0;
-  while (! mii.isBranch(termMvec[first]->getOpCode()) &&
-         ! mii.isReturn(termMvec[first]->getOpCode()))
+  while (! mii.isBranch(termMvec[first]->getOpcode()) &&
+         ! mii.isReturn(termMvec[first]->getOpcode()))
     ++first;
   assert(first < termMvec.size() &&
 	 "No branch instructions for terminator?  Ok, but weird!");
@@ -159,8 +159,8 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
     assert(toNode && "No node for instr generated for branch/ret?");
     
     for (unsigned j = i-1; j != 0; --j) 
-      if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
-          mii.isReturn(termMvec[j-1]->getOpCode())) {
+      if (mii.isBranch(termMvec[j-1]->getOpcode()) ||
+          mii.isReturn(termMvec[j-1]->getOpcode())) {
         SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
         assert(brNode && "No node for instr generated for branch/ret?");
         (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
@@ -198,7 +198,7 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
     // the terminator) that also have delay slots, add an outgoing edge
     // from the instruction to the instructions in the delay slots.
     // 
-    unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
+    unsigned d = mii.getNumDelaySlots(MBB[i]->getOpcode());
     assert(i+d < N && "Insufficient delay slots for instruction?");
       
     for (unsigned j=1; j <= d; j++) {
@@ -242,12 +242,12 @@ void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
   // 
   for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
-    MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
+    MachineOpCode fromOpCode = memNodeVec[im]->getOpcode();
     int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
                     : (mii.isLoad(fromOpCode)? SG_LOAD_REF
                        : SG_STORE_REF));
     for (unsigned jm=im+1; jm < NM; jm++) {
-      MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
+      MachineOpCode toOpCode = memNodeVec[jm]->getOpcode();
       int toType = (mii.isCall(toOpCode)? SG_CALL_REF
                     : (mii.isLoad(toOpCode)? SG_LOAD_REF
                        : SG_STORE_REF));
@@ -274,7 +274,7 @@ void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNode
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
   // 
   for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
-    if (mii.isCall(callDepNodeVec[ic]->getOpCode())) {
+    if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
       // Add SG_CALL_REF edges from all preds to this instruction.
       for (unsigned jc=0; jc < ic; jc++)
 	(void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
@@ -292,7 +292,7 @@ void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNode
   // Find the call instruction nodes and put them in a vector.
   std::vector<SchedGraphNode*> callNodeVec;
   for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
-    if (mii.isCall(memNodeVec[im]->getOpCode()))
+    if (mii.isCall(memNodeVec[im]->getOpcode()))
       callNodeVec.push_back(memNodeVec[im]);
   
   // Now walk the entire basic block, looking for CC instructions *and*
@@ -302,14 +302,14 @@ void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNode
   // 
   int lastCallNodeIdx = -1;
   for (unsigned i=0, N=bbMvec.size(); i < N; i++)
-    if (mii.isCall(bbMvec[i]->getOpCode())) {
+    if (mii.isCall(bbMvec[i]->getOpcode())) {
       ++lastCallNodeIdx;
       for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
         if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
           break;
       assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
     }
-    else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
+    else if (mii.isCCInstr(bbMvec[i]->getOpcode())) {
       // Add incoming/outgoing edges from/to preceding/later calls
       SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
       int j=0;
@@ -469,7 +469,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
 				       ValueToDefVecMap& valueToDefVecMap) {
   const TargetInstrInfo& mii = target.getInstrInfo();
   
-  MachineOpCode opCode = node->getOpCode();
+  MachineOpCode opCode = node->getOpcode();
   
   if (mii.isCall(opCode) || mii.isCCInstr(opCode))
     callDepNodeVec.push_back(node);
@@ -554,7 +554,7 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.
   for (unsigned i=0; i < MBB.size(); i++)
-    if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
+    if (!mii.isDummyPhiInstr(MBB[i]->getOpcode())) {
       SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
       noteGraphNodeForInstr(MBB[i], node);
       
diff --git a/lib/CodeGen/InstrSched/SchedGraph.h b/lib/CodeGen/InstrSched/SchedGraph.h
index 18b2a3f..e327598 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.h
+++ b/lib/CodeGen/InstrSched/SchedGraph.h
@@ -48,7 +48,7 @@ public:
 
   // Accessor methods
   const MachineInstr* getMachineInstr() const { return MI; }
-  const MachineOpCode getOpCode() const { return MI->getOpCode(); }
+  const MachineOpCode getOpcode() const { return MI->getOpcode(); }
   bool isDummyNode() const { return (MI == NULL); }
   MachineBasicBlock &getMachineBasicBlock() const { return *MBB; }
 
diff --git a/lib/CodeGen/InstrSched/SchedPriorities.cpp b/lib/CodeGen/InstrSched/SchedPriorities.cpp
index 7e05d14..b5bc38e 100644
--- a/lib/CodeGen/InstrSched/SchedPriorities.cpp
+++ b/lib/CodeGen/InstrSched/SchedPriorities.cpp
@@ -211,7 +211,7 @@ SchedPriorities::getNextHighest(const SchedulingManager& S,
     // it becomes empty.
     nextChoice = candsAsHeap.getNode(mcands[nextIdx]);
     if (getEarliestReadyTimeForNode(nextChoice) > curTime
-        || ! instrIsFeasible(S, nextChoice->getMachineInstr()->getOpCode()))
+        || ! instrIsFeasible(S, nextChoice->getMachineInstr()->getOpcode()))
     {
       mcands.erase(mcands.begin() + nextIdx);
       nextIdx = -1;
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 9cec481..7d2ecec 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -424,7 +424,7 @@ public:
     // Append the instruction to the vector of choices for current cycle.
     // Increment numInClass[c] for the sched class to which the instr belongs.
     choiceVec.push_back(node);
-    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
+    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
     assert(sc < numInClass.size());
     numInClass[sc]++;
   }
@@ -478,7 +478,7 @@ public:
       choicesForSlot[s].erase(node);
     
     // and decrement the instr count for the sched class to which it belongs
-    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpCode());
+    const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
     assert(sc < numInClass.size());
     numInClass[sc]--;
   }
@@ -498,7 +498,7 @@ public:
     if (!createIfMissing) return 0;
 
     DelaySlotInfo *dinfo =
-      new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpCode()));
+      new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpcode()));
     return delaySlotInfoForBranches[bn] = dinfo;
   }
   
@@ -537,19 +537,19 @@ void
 SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
 					    cycles_t schedTime)
 {
-  if (schedInfo.numBubblesAfter(node->getOpCode()) > 0)
+  if (schedInfo.numBubblesAfter(node->getOpcode()) > 0)
     { // Update next earliest time before which *nothing* can issue.
       nextEarliestIssueTime = std::max(nextEarliestIssueTime,
-		  curTime + 1 + schedInfo.numBubblesAfter(node->getOpCode()));
+		  curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
     }
   
   const std::vector<MachineOpCode>&
-    conflictVec = schedInfo.getConflictList(node->getOpCode());
+    conflictVec = schedInfo.getConflictList(node->getOpcode());
   
   for (unsigned i=0; i < conflictVec.size(); i++)
     {
       MachineOpCode toOp = conflictVec[i];
-      cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpCode(),toOp);
+      cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpcode(),toOp);
       assert(toOp < (int) nextEarliestStartTime.size());
       if (nextEarliestStartTime[toOp] < est)
         nextEarliestStartTime[toOp] = est;
@@ -630,8 +630,8 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   // some NOPs from delay slots.  Also, PHIs are not included in the schedule.
   unsigned numInstr = 0;
   for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
-    if (! mii.isNop((*I)->getOpCode()) &&
-	! mii.isDummyPhiInstr((*I)->getOpCode()))
+    if (! mii.isNop((*I)->getOpcode()) &&
+	! mii.isDummyPhiInstr((*I)->getOpcode()))
       ++numInstr;
   assert(S.isched.getNumInstructions() >= numInstr &&
 	 "Lost some non-NOP instructions during scheduling!");
@@ -643,7 +643,7 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   // First find the dummy instructions at the start of the basic block
   MachineBasicBlock::iterator I = MBB.begin();
   for ( ; I != MBB.end(); ++I)
-    if (! mii.isDummyPhiInstr((*I)->getOpCode()))
+    if (! mii.isDummyPhiInstr((*I)->getOpcode()))
       break;
   
   // Erase all except the dummy PHI instructions from MBB, and
@@ -726,7 +726,7 @@ FindSlotChoices(SchedulingManager& S,
     if (nextNode == NULL)
       break;			// no more instructions for this cycle
       
-    if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpCode()) > 0) {
+    if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) {
       delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
       if (delaySlotInfo != NULL) {
         if (indexForBreakingNode < S.nslots)
@@ -736,7 +736,7 @@ FindSlotChoices(SchedulingManager& S,
         else
           indexForDelayedInstr = S.getNumChoices();
       }
-    } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpCode())) {
+    } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpcode())) {
       if (indexForBreakingNode < S.nslots)
         // have a breaking instruction already so throw this one away
         nextNode = NULL;
@@ -747,7 +747,7 @@ FindSlotChoices(SchedulingManager& S,
     if (nextNode != NULL) {
       S.addChoice(nextNode);
       
-      if (S.schedInfo.isSingleIssue(nextNode->getOpCode())) {
+      if (S.schedInfo.isSingleIssue(nextNode->getOpcode())) {
         assert(S.getNumChoices() == 1 &&
                "Prioritizer returned invalid instr for this cycle!");
         break;
@@ -772,7 +772,7 @@ FindSlotChoices(SchedulingManager& S,
     // This is the common case, so handle it separately for efficiency.
       
     if (S.getNumChoices() == 1) {
-      MachineOpCode opCode = S.getChoice(0)->getOpCode();
+      MachineOpCode opCode = S.getChoice(0)->getOpcode();
       unsigned int s;
       for (s=startSlot; s < S.nslots; s++)
         if (S.schedInfo.instrCanUseSlot(opCode, s))
@@ -781,7 +781,7 @@ FindSlotChoices(SchedulingManager& S,
       S.addChoiceToSlot(s, S.getChoice(0));
     } else {
       for (unsigned i=0; i < S.getNumChoices(); i++) {
-        MachineOpCode opCode = S.getChoice(i)->getOpCode();
+        MachineOpCode opCode = S.getChoice(i)->getOpcode();
         for (unsigned int s=startSlot; s < S.nslots; s++)
           if (S.schedInfo.instrCanUseSlot(opCode, s))
             S.addChoiceToSlot(s, S.getChoice(i));
@@ -799,7 +799,7 @@ FindSlotChoices(SchedulingManager& S,
     assert(delaySlotInfo != NULL && "No delay slot info for instr?");
       
     const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
-    MachineOpCode delayOpCode = delayedNode->getOpCode();
+    MachineOpCode delayOpCode = delayedNode->getOpcode();
     unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
       
     unsigned delayedNodeSlot = S.nslots;
@@ -817,7 +817,7 @@ FindSlotChoices(SchedulingManager& S,
     for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
       // Try to assign every other instruction to a lower numbered
       // slot than delayedNodeSlot.
-      MachineOpCode opCode =S.getChoice(i)->getOpCode();
+      MachineOpCode opCode =S.getChoice(i)->getOpcode();
       bool noSlotFound = true;
       unsigned int s;
       for (s=startSlot; s < delayedNodeSlot; s++)
@@ -867,7 +867,7 @@ FindSlotChoices(SchedulingManager& S,
 	  
     // Find the last possible slot for this instruction.
     for (int s = S.nslots-1; s >= (int) startSlot; s--)
-      if (S.schedInfo.instrCanUseSlot(breakingNode->getOpCode(), s)) {
+      if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
         breakingSlot = s;
         break;
       }
@@ -880,7 +880,7 @@ FindSlotChoices(SchedulingManager& S,
     for (unsigned i=0;
          i < S.getNumChoices() && i < indexForBreakingNode; i++)
     {
-      MachineOpCode opCode =S.getChoice(i)->getOpCode();
+      MachineOpCode opCode =S.getChoice(i)->getOpcode();
 	  
       // If a higher priority instruction cannot be assigned to
       // any earlier slots, don't schedule the breaking instruction.
@@ -914,7 +914,7 @@ FindSlotChoices(SchedulingManager& S,
     // group, only assign them to slots lower than the breaking slot.
     // Otherwise, just ignore the instruction.
     for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) {
-      MachineOpCode opCode = S.getChoice(i)->getOpCode();
+      MachineOpCode opCode = S.getChoice(i)->getOpcode();
       for (unsigned int s=startSlot; s < nslotsToUse; s++)
         if (S.schedInfo.instrCanUseSlot(opCode, s))
           S.addChoiceToSlot(s, S.getChoice(i));
@@ -1026,11 +1026,11 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
   assert(! node->isDummyNode());
   
   // don't put a branch in the delay slot of another branch
-  if (S.getInstrInfo().isBranch(node->getOpCode()))
+  if (S.getInstrInfo().isBranch(node->getOpcode()))
     return false;
   
   // don't put a single-issue instruction in the delay slot of a branch
-  if (S.schedInfo.isSingleIssue(node->getOpCode()))
+  if (S.schedInfo.isSingleIssue(node->getOpcode()))
     return false;
   
   // don't put a load-use dependence in the delay slot of a branch
@@ -1039,13 +1039,13 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
   for (SchedGraphNode::const_iterator EI = node->beginInEdges();
        EI != node->endInEdges(); ++EI)
     if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode()
-	&& mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpCode())
+	&& mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
 	&& (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
       return false;
   
   // for now, don't put an instruction that does not have operand
   // interlocks in the delay slot of a branch
-  if (! S.getInstrInfo().hasOperandInterlock(node->getOpCode()))
+  if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode()))
     return false;
   
   // Finally, if the instruction precedes the branch, we make sure the
@@ -1102,7 +1102,7 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
 {
   const TargetInstrInfo& mii = S.getInstrInfo();
   unsigned ndelays =
-    mii.getNumDelaySlots(brNode->getOpCode());
+    mii.getNumDelaySlots(brNode->getOpcode());
   
   if (ndelays == 0)
     return;
@@ -1117,10 +1117,10 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
   for (sg_pred_iterator P = pred_begin(brNode);
        P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
     if (! (*P)->isDummyNode() &&
-	! mii.isNop((*P)->getOpCode()) &&
+	! mii.isNop((*P)->getOpcode()) &&
 	NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
     {
-      if (mii.maxLatency((*P)->getOpCode()) > 1)
+      if (mii.maxLatency((*P)->getOpcode()) > 1)
         mdelayNodeVec.push_back(*P);
       else
         sdelayNodeVec.push_back(*P);
@@ -1133,12 +1133,12 @@ FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
   // 
   while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
     unsigned lmin =
-      mii.maxLatency(mdelayNodeVec[0]->getOpCode());
+      mii.maxLatency(mdelayNodeVec[0]->getOpcode());
     unsigned minIndex   = 0;
     for (unsigned i=1; i < mdelayNodeVec.size(); i++)
     {
       unsigned li = 
-        mii.maxLatency(mdelayNodeVec[i]->getOpCode());
+        mii.maxLatency(mdelayNodeVec[i]->getOpcode());
       if (lmin >= li)
       {
         lmin = li;
@@ -1166,7 +1166,7 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
   std::vector<SchedGraphNode*> nopNodeVec;   // this will hold unused NOPs
   const TargetInstrInfo& mii = S.getInstrInfo();
   const MachineInstr* brInstr = node->getMachineInstr();
-  unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
+  unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpcode());
   assert(ndelays > 0 && "Unnecessary call to replace NOPs");
   
   // Remove the NOPs currently in delay slots from the graph.
@@ -1182,14 +1182,14 @@ static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
   // and USE THEM.  We'll throw away the unused alternatives below
   // 
   for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
-    if (! mii.isNop(MBB[i]->getOpCode()))
+    if (! mii.isNop(MBB[i]->getOpcode()))
       sdelayNodeVec.insert(sdelayNodeVec.begin(),
                            graph->getGraphNodeForInstr(MBB[i]));
   
   // Then find the NOPs and keep only as many as are needed.
   // Put the rest in nopNodeVec to be deleted.
   for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
-    if (mii.isNop(MBB[i]->getOpCode()))
+    if (mii.isNop(MBB[i]->getOpcode()))
       if (sdelayNodeVec.size() < ndelays)
         sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
       else {
@@ -1256,7 +1256,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
     // 
     unsigned first = 0;
     while (first < termMvec.size() &&
-           ! mii.isBranch(termMvec[first]->getOpCode()))
+           ! mii.isBranch(termMvec[first]->getOpcode()))
     {
       ++first;
     }
@@ -1283,7 +1283,7 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
   delayNodeVec.clear();
   for (unsigned i=0; i < MBB.size(); ++i)
     if (MBB[i] != brInstr &&
-        mii.getNumDelaySlots(MBB[i]->getOpCode()) > 0)
+        mii.getNumDelaySlots(MBB[i]->getOpcode()) > 0)
     {
       SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
       ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
@@ -1321,10 +1321,10 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
     for (unsigned i=0; i < delayNodeVec.size(); i++) {
       const SchedGraphNode* dnode = delayNodeVec[i];
       if ( ! S.isScheduled(dnode)
-           && S.schedInfo.instrCanUseSlot(dnode->getOpCode(), nextSlot)
-           && instrIsFeasible(S, dnode->getOpCode()))
+           && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
+           && instrIsFeasible(S, dnode->getOpcode()))
       {
-        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpCode())
+        assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode())
                && "Instructions without interlocks not yet supported "
                "when filling branch delay slots");
         S.scheduleInstr(dnode, nextSlot, nextTime);
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 65f1511..fe150c2 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -55,7 +55,7 @@ SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
                                int   indexInBB, const TargetMachine& Target)
   : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
   if (MI) {
-    MachineOpCode mopCode = MI->getOpCode();
+    MachineOpCode mopCode = MI->getOpcode();
     latency = Target.getInstrInfo().hasResultInterlock(mopCode)
       ? Target.getInstrInfo().minLatency(mopCode)
       : Target.getInstrInfo().maxLatency(mopCode);
@@ -140,8 +140,8 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
   // Find the first branch instr in the sequence of machine instrs for term
   // 
   unsigned first = 0;
-  while (! mii.isBranch(termMvec[first]->getOpCode()) &&
-         ! mii.isReturn(termMvec[first]->getOpCode()))
+  while (! mii.isBranch(termMvec[first]->getOpcode()) &&
+         ! mii.isReturn(termMvec[first]->getOpcode()))
     ++first;
   assert(first < termMvec.size() &&
 	 "No branch instructions for terminator?  Ok, but weird!");
@@ -159,8 +159,8 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
     assert(toNode && "No node for instr generated for branch/ret?");
     
     for (unsigned j = i-1; j != 0; --j) 
-      if (mii.isBranch(termMvec[j-1]->getOpCode()) ||
-          mii.isReturn(termMvec[j-1]->getOpCode())) {
+      if (mii.isBranch(termMvec[j-1]->getOpcode()) ||
+          mii.isReturn(termMvec[j-1]->getOpcode())) {
         SchedGraphNode* brNode = getGraphNodeForInstr(termMvec[j-1]);
         assert(brNode && "No node for instr generated for branch/ret?");
         (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
@@ -198,7 +198,7 @@ void SchedGraph::addCDEdges(const TerminatorInst* term,
     // the terminator) that also have delay slots, add an outgoing edge
     // from the instruction to the instructions in the delay slots.
     // 
-    unsigned d = mii.getNumDelaySlots(MBB[i]->getOpCode());
+    unsigned d = mii.getNumDelaySlots(MBB[i]->getOpcode());
     assert(i+d < N && "Insufficient delay slots for instruction?");
       
     for (unsigned j=1; j <= d; j++) {
@@ -242,12 +242,12 @@ void SchedGraph::addMemEdges(const std::vector<SchedGraphNode*>& memNodeVec,
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
   // 
   for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++) {
-    MachineOpCode fromOpCode = memNodeVec[im]->getOpCode();
+    MachineOpCode fromOpCode = memNodeVec[im]->getOpcode();
     int fromType = (mii.isCall(fromOpCode)? SG_CALL_REF
                     : (mii.isLoad(fromOpCode)? SG_LOAD_REF
                        : SG_STORE_REF));
     for (unsigned jm=im+1; jm < NM; jm++) {
-      MachineOpCode toOpCode = memNodeVec[jm]->getOpCode();
+      MachineOpCode toOpCode = memNodeVec[jm]->getOpcode();
       int toType = (mii.isCall(toOpCode)? SG_CALL_REF
                     : (mii.isLoad(toOpCode)? SG_LOAD_REF
                        : SG_STORE_REF));
@@ -274,7 +274,7 @@ void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNode
   // so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
   // 
   for (unsigned ic=0, NC=callDepNodeVec.size(); ic < NC; ic++)
-    if (mii.isCall(callDepNodeVec[ic]->getOpCode())) {
+    if (mii.isCall(callDepNodeVec[ic]->getOpcode())) {
       // Add SG_CALL_REF edges from all preds to this instruction.
       for (unsigned jc=0; jc < ic; jc++)
 	(void) new SchedGraphEdge(callDepNodeVec[jc], callDepNodeVec[ic],
@@ -292,7 +292,7 @@ void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNode
   // Find the call instruction nodes and put them in a vector.
   std::vector<SchedGraphNode*> callNodeVec;
   for (unsigned im=0, NM=memNodeVec.size(); im < NM; im++)
-    if (mii.isCall(memNodeVec[im]->getOpCode()))
+    if (mii.isCall(memNodeVec[im]->getOpcode()))
       callNodeVec.push_back(memNodeVec[im]);
   
   // Now walk the entire basic block, looking for CC instructions *and*
@@ -302,14 +302,14 @@ void SchedGraph::addCallDepEdges(const std::vector<SchedGraphNode*>& callDepNode
   // 
   int lastCallNodeIdx = -1;
   for (unsigned i=0, N=bbMvec.size(); i < N; i++)
-    if (mii.isCall(bbMvec[i]->getOpCode())) {
+    if (mii.isCall(bbMvec[i]->getOpcode())) {
       ++lastCallNodeIdx;
       for ( ; lastCallNodeIdx < (int)callNodeVec.size(); ++lastCallNodeIdx)
         if (callNodeVec[lastCallNodeIdx]->getMachineInstr() == bbMvec[i])
           break;
       assert(lastCallNodeIdx < (int)callNodeVec.size() && "Missed Call?");
     }
-    else if (mii.isCCInstr(bbMvec[i]->getOpCode())) {
+    else if (mii.isCCInstr(bbMvec[i]->getOpcode())) {
       // Add incoming/outgoing edges from/to preceding/later calls
       SchedGraphNode* ccNode = this->getGraphNodeForInstr(bbMvec[i]);
       int j=0;
@@ -469,7 +469,7 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
 				       ValueToDefVecMap& valueToDefVecMap) {
   const TargetInstrInfo& mii = target.getInstrInfo();
   
-  MachineOpCode opCode = node->getOpCode();
+  MachineOpCode opCode = node->getOpcode();
   
   if (mii.isCall(opCode) || mii.isCCInstr(opCode))
     callDepNodeVec.push_back(node);
@@ -554,7 +554,7 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.
   for (unsigned i=0; i < MBB.size(); i++)
-    if (!mii.isDummyPhiInstr(MBB[i]->getOpCode())) {
+    if (!mii.isDummyPhiInstr(MBB[i]->getOpcode())) {
       SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
       noteGraphNodeForInstr(MBB[i], node);
       
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.h b/lib/Target/SparcV9/InstrSched/SchedGraph.h
index 18b2a3f..e327598 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.h
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.h
@@ -48,7 +48,7 @@ public:
 
   // Accessor methods
   const MachineInstr* getMachineInstr() const { return MI; }
-  const MachineOpCode getOpCode() const { return MI->getOpCode(); }
+  const MachineOpCode getOpcode() const { return MI->getOpcode(); }
   bool isDummyNode() const { return (MI == NULL); }
   MachineBasicBlock &getMachineBasicBlock() const { return *MBB; }
 
diff --git a/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp b/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp
index 7e05d14..b5bc38e 100644
--- a/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp
@@ -211,7 +211,7 @@ SchedPriorities::getNextHighest(const SchedulingManager& S,
     // it becomes empty.
     nextChoice = candsAsHeap.getNode(mcands[nextIdx]);
     if (getEarliestReadyTimeForNode(nextChoice) > curTime
-        || ! instrIsFeasible(S, nextChoice->getMachineInstr()->getOpCode()))
+        || ! instrIsFeasible(S, nextChoice->getMachineInstr()->getOpcode()))
     {
       mcands.erase(mcands.begin() + nextIdx);
       nextIdx = -1;